Antony AbeePrakash X V wrote:
> This time I tried with verbose option and the output is below
> $ ./cbmem -V -t
..
> Failed to mmap /dev/mem: Operation not permitted
You have to run that command as root. Regular users are not allowed
arbitrary access to memory.
//Peter
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coreboot mailing
rbin [mailto:adur...@google.com]
Sent: Thursday, October 11, 2018 9:44 PM
To: Antony AbeePrakash X V
Cc: Coreboot ; Dinesh Kumar
Subject: Re: [coreboot] MRC in coreboot
cbmem timstamps will be needed.
Looks like FSP is manipulating the tsc:
BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 4291539104 ex
: [coreboot] MRC in coreboot
On Fri, Oct 12, 2018 at 4:38 AM Antony AbeePrakash X V
mailto:antonyabee.prakas...@lnttechservices.com>>
wrote:
Hi Aron,
I am not able to get the cbmem timestamps. I am using cbmem utility to find the
timestamps.
$ . /cbmem -t
The above command gives the following
ESERVED
How old of a cbmem utility are you using? don't understand where the
1MiB mappings are coming from.
>
>
>
> Thanks,
>
> Antony
>
>
>
> From: Aaron Durbin [mailto:adur...@google.com]
> Sent: Friday, October 12, 2018 7:12 PM
> To: Antony AbeePraka
h X V
> *Cc:* Coreboot ; Dinesh Kumar <
> dineshkumar.varadara...@lnttechservices.com>
> *Subject:* Re: [coreboot] MRC in coreboot
>
>
>
> cbmem timstamps will be needed.
>
>
>
> Looks like FSP is manipulating the tsc:
>
> BS: BS_DEV_INIT_CHIPS times (us): en
: [coreboot] MRC in coreboot
On Thu, Oct 11, 2018 at 3:24 AM Antony AbeePrakash X V
wrote:
>
> Hi All,
>
> We are able to achieve the memory initialization time reduction. Now we have
> achieved the boot time as 5sec until the Postcode 0xf8 (entry into Elf boot).
>
> We have
be done further ?
Thanks,
Antony
-Original Message-
From: Aaron Durbin [mailto:adur...@google.com]
Sent: Wednesday, September 05, 2018 7:39 PM
To: Antony AbeePrakash X V
Cc: Coreboot
Subject: Re: [coreboot] MRC in coreboot
On Wed, Sep 5, 2018 at 8:06 AM Antony AbeePrakash X V
wrote
t; To: Antony AbeePrakash X V
> Cc: Coreboot ; Dinesh Kumar <
> dineshkumar.varadara...@lnttechservices.com>
> Subject: Re: [coreboot] MRC in coreboot
>
> On Thu, Oct 11, 2018 at 3:24 AM Antony AbeePrakash X V <
> antonyabee.prakas...@lnttechservices.com> wrote:
&g
in [mailto:adur...@google.com]
> Sent: Wednesday, September 05, 2018 7:39 PM
> To: Antony AbeePrakash X V
> Cc: Coreboot
> Subject: Re: [coreboot] MRC in coreboot
>
> On Wed, Sep 5, 2018 at 8:06 AM Antony AbeePrakash X V
> wrote:
> >
> > Hi,
> >
> >
On Wed, Sep 5, 2018 at 8:06 AM Antony AbeePrakash X V
wrote:
>
> Hi,
>
>
>
> We are developing coreboot for Apollo lake custom board. MRC training data
> save is enabled in FSP using Binary configuration tool.
>
>
>
> But we are getting logs like,
>
>
>
> No MRC cache found.
>
> MRC SeCUmaSize
Hi,
We are developing coreboot for Apollo lake custom board. MRC training data
save is enabled in FSP using Binary configuration tool.
But we are getting logs like,
No MRC cache found.
MRC SeCUmaSize memory size from SeC ... 0
MRC Parameters not valid. Status is Success
MRC:CpuMemoryTest
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