Hi Jose, All,
I built coreboot.rom with the right microcode.
Following is the coreboot build summary:
***
Name OffsetType
Size Comp
cbfs master header 0x0
Zvika:
The microcode you downloaded doesn't include the binary for your system... read
the release notes.
6, 55, 9 = 06-37-09
Download this:
https://github.com/platomav/CPUMicrocodes/blob/master/Intel/cpu30679_plat0F_ver090A_2018-01-10_PRD_252563C5.bin
Rename this bin to:06-37-09
Hi Jose,
In menuconfig I have the following options in "Include CPU microcode in
CBFS"
1. Generate from tree (current selection)
2. Include external microcode header files
3. Do not include microcode updates
I downloaded the file: microcode-20180807a.tgz
The output of /proc/cpuinfo is:
Good day Zvika:
Looks typical the configuration
But for DIMM Density to get this information you should run the command I told
you yesterday or check the memory chip datasheet.
About the 0xCE postcode you need to set the microcode (or the correct one, or
the correct path) in menuconfig.
Jose.
Hi Jose, All,
According to the following outputs, it seems my target has SPD EEPROM.
If I understand correctly from your reply, I should modify only:
DRAM Type: DDR3
DRAM Speed: 1333 MT/s
DIMM 0 Enable: Enabled
DIMM 1 Enable: Disabled
DIMM_DWidth: x8
DIMM_Density: ??? (Default is 2Gbit)
Zvika:
In my experience with my Baytrail system I can tell you my system is "really"
memory down because has soldered memory chips on the motherboard BUT has also a
soldered SPD memory so, if keep "Enable Memory Down = Disabled" in BCT the
system fetch memory timings from SPD so, no need to
Hello,
The BCT has a "Memory Down" section.
Can you please advise how can I know the right values for my board ?
DIMM 0/1 Enable:
DIMM DWidth:
DIMM Density:
DIMM_BusWidth:
DIMM Sides:
tCL:
tRP_tRCD:
tWR:
tWTR:
tRRD:
tRTP:
tFAW:
Thank you in advance,
Zvika
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