ron minnich [mailto:rminn...@gmail.com] wrote:
]On Tue, May 13, 2014 at 5:29 AM, Peter Stuge pe...@stuge.se wrote:
]
] That's an important question, but I believe the answer is no.
]
]That's all I wanted to know, to start.
]
]So why don't we just get that CL in and see where we go from there.
]
ron minnich wrote:
Why shouldn't coreboot do legacy initialization? What is the reason
to be *less* compatible than possible?
The main question I had was whether enabling this set of interrupts
could negatively impact other payloads.
That's an important question, but I believe the answer
On Tue, May 13, 2014 at 5:29 AM, Peter Stuge pe...@stuge.se wrote:
That's an important question, but I believe the answer is no.
That's all I wanted to know, to start.
So why don't we just get that CL in and see where we go from there.
Thanks all. And sorry if I was too hard on kolibrios.
ron minnich wrote:
I'm not really happy that we're doing all this PIC setup for one OS,
It's not for one OS, Ron. PIC setup is part of the PC legacy.
Please remember that coreboot is more than Chrome OS' firmware of choice.
It's been quite some time since I've had to use PIC mode at all.
On Mon, May 12, 2014 at 09:13:26PM +0200, Peter Stuge wrote:
ron minnich wrote:
I'm not really happy that we're doing all this PIC setup for one OS,
It's not for one OS, Ron. PIC setup is part of the PC legacy.
Please remember that coreboot is more than Chrome OS' firmware of choice.
On Mon, May 12, 2014 at 12:13 PM, Peter Stuge pe...@stuge.se wrote:
Why shouldn't coreboot do legacy initialization? What is the reason
to be *less* compatible than possible?
The main question I had was whether enabling this set of interrupts
could negatively impact other payloads. The goal of
Hi all,
1) we should provide at least the MP-Table. There is a still lot of OS without
ACPI support (various homebrew OS, RTOS etc) which don't want to carry the
ACPICA just to get idea how to route IRQs...
2) if we want to setup the PCI for PIC we need to do:
a) setup the PCI router (just
Like I say, if it's not going to do harm, and you all want it, submit the CL.
ron
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Hi Scott!
The NIC
bus number is hard-coded at the moment. This needs fixing
if the NIC bus number can change.
The bus number of the NIC changed from 03:00.0 to 04:00.0 when I plugged
a PCIe card into the board. Tried that maybe two weeks ago.
Regards
Felix
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coreboot mailing list:
Scott Duplichan [mailto:sc...@notabs.org] wrote:
[...]
]As for the mouse problem, I think it may be PIC interrupt
]routing related. I see our PIR table is incomplete and also
]the legacy interrupting route reporting registers in PCI
]config space are not filled in. I will look at that tomorrow.
So, how would these changes affect other payloads?
ron
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ron minnich [mailto:rminn...@gmail.com] wrote:
]So, how would these changes affect other payloads?
]
]ron
The patch adds programming and one reporting
mechanism for PIC mode PCI interrupt routing for
the ASRock E350M1 board only. Without the patch,
PIC mode PCI interrupt routing is not
Thanks, that's a great explanation. Generally, we've tried to avoid
too much hardware setup in coreboot; that's the job of the kernel. I'm
not really happy that we're doing all this PIC setup for one OS,
written in assembly. It's been quite some time since I've had to use
PIC mode at all.
Why
ron minnich [mailto:rminn...@gmail.com] wrote:
]Thanks, that's a great explanation. Generally, we've tried to avoid
]too much hardware setup in coreboot; that's the job of the kernel.
The PIC mode interrupt routing configuration must be done by
BIOS because proprietary southbridge registers are
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