On Tue, Apr 10, 2012 at 10:19 AM, Stefan Reinauer
wrote:
> On 4/10/12 11:13 PM, Marc Jones wrote:
>>
>> Stefan, can you explain the requirement or consider how else to only do
>> this on a processor that requires it?Marc
>
> I will try to reconstruct how this was needed. I might not have the test
On 4/10/12 11:13 PM, Marc Jones wrote:
Stefan, can you explain the requirement or consider how else to only
do this on a processor that requires it?Marc
I will try to reconstruct how this was needed. I might not have the test
system anymore. If it works without now, we should drop that patch ag
t; Cc: 'Marc Jones'; Marc Jones; 'coreboot@coreboot.org'
>> Subject: Re: [coreboot] Patch merged into coreboot/master: c35c461
>> Invalidate cache before first jump
>>
>> On 09/04/12 04:24, Bao, Zheng wrote:
>> > Hi,
>> > It is unstable. In
[coreboot] Patch merged into coreboot/master: c35c461
> Invalidate cache before first jump
>
> On 09/04/12 04:24, Bao, Zheng wrote:
> > Hi,
> > It is unstable. In most cases, it hangs at this wbinvd. Once it pass
> that instruction, it will hang at when AP cores are launche
On 09/04/12 04:24, Bao, Zheng wrote:
Hi,
It is unstable. In most cases, it hangs at this wbinvd. Once it pass that
instruction, it will hang at when AP cores are launched.
Try invd instead of wbinvd. There should be no need to preserve anything
from the cache so the write back is not needed.
t; Cc: coreboot@coreboot.org; Marc Jones
> Subject: Re: [coreboot] Patch merged into coreboot/master: c35c461
> Invalidate cache before first jump
>
> Can you be more descriptive to how it fails? Does it hang on that
> instruction?
>
> Marc
>
>
> On Fri, Apr 6, 2012 at 5:38
I'm not sure why it would be breaking anything, but it just doesn't
make sense. From Volume 3:
"Because all internal cache lines are invalid following reset
initialization, it is not necessary to invalidate the cache before
enabling caching."
It is pretty weird, I downloaded one random Sandybridge
Am 06.04.2012 20:26, schrieb Stefan Reinauer:
>> That change might also break on future CPUs (if they finally manage
>> to make the TPM stuff secure, so that's a big if)
> How so?
Load top x KB into cache, let the CPU measure the data from cache into a
PCR, run the code from cache (to avoid TOCTOU
* Patrick Georgi [120406 17:32]:
> Am 06.04.2012 17:27, schrieb Marc Jones:
> > Can you be more descriptive to how it fails? Does it hang on that
> > instruction?
> That change might also break on future CPUs (if they finally manage
> to make the TPM stuff secure, so that's a big if)
How so?
Gue
Am 06.04.2012 17:27, schrieb Marc Jones:
> Can you be more descriptive to how it fails? Does it hang on that
> instruction?
That change might also break on future CPUs (if they finally manage
to make the TPM stuff secure, so that's a big if)
Patrick
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>> boun...@coreboot.org] On Behalf Of ger...@coreboot.org
>> Sent: Friday, April 06, 2012 5:03 AM
>> To: coreboot@coreboot.org
>> Subject: [coreboot] Patch merged into coreboot/master: c35c461
>> Invalidate cache before first jump
>>
&g
Subject: [coreboot] Patch merged into coreboot/master: c35c461
> Invalidate cache before first jump
>
> the following patch was just integrated into master:
> commit c35c461bb2146ab949062f22e265406deef178d2
> Author: Stefan Reinauer
> Date: Tue Apr 3 16:09:46 2012 -0700
>
&
the following patch was just integrated into master:
commit c35c461bb2146ab949062f22e265406deef178d2
Author: Stefan Reinauer
Date: Tue Apr 3 16:09:46 2012 -0700
Invalidate cache before first jump
Some CPUs (Sandybridge) seem to require this, and it does not hurt
on other CPUs.
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