Dear Jose,
I felt that you are very close to resolving it and it is some minor
issue not exactly in the Super I/O init code.
Great job and good luck with future challenges.
And of course enjoy coreboot!
Best regards,
--
Michał Żygowski
Firmware Engineer
https://3mdeb.com | @3mdeb_com
On
Dear Michal:
Thank you very much for all your guidance.
The problem was resolved.
The code was OK but was not executed at the right time (was executed before LPC
and SIO were initialized).
The attached code did the job
Have a great day.
Jose Trujillo.
‐‐‐ Original Message ‐‐‐
On
Thank you Michal:
(you) Just use the appropriate 0xa00 base +
REG OFFSET from the table and you should be allright.
(Me) This is what I believe I did: 0xa00 + 0x040 = GP51/DCD_2 Function Select.
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Maybe I am not setting the code in the right place or executing at the right
time?
Hi Jose,
>
> and I do similar to you under romstage.c -> mainboard_early_init:
>
> outb(0x55, 0x2e);
> outb(0x05, 0x0a3f); /* GP50= RI_2 : in */
> outb(0x05, 0x0a40); /* GP51= DCD_2 : in */
> outb(0x05, 0x0a41); /* GP52= RXD_2 : in */
> outb(0x04, 0x0a42); /* GP53= TXD_2 : out */
> outb(0x05,
Dear Michal,
I am sorry for the late reply but on Friday something went wrong with my
coreboot installation and was unable to boot and I have to reinstall it again
and I just resumed this morning on this issue.
(you) don't think loading the watchdog module will help in any way, actually
the
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