;>
>> Thanks,
>>
>> *Laurie*
>>
>>
>>
>> laurie.jarlst...@intel.com,
>>
>> System Firmware Products
>>
>> Firmware Ecosystem & Business Dev.
>>
>> (503) 880 5648 Mobile
>>
>>
>>
>> *From:* ro
*Sent:* Friday, September 30, 2022 9:00 AM
> *To:* Nico Huber
> *Cc:* Arthur Heymans ; coreboot <
> coreboot@coreboot.org>
> *Subject:* [coreboot] Re: FSP 2.4: runtime blobs!
>
>
>
> note that I am having this exact same problem in the RISC-V community:
> https://github.
system & Business Dev.
(503) 880 5648 Mobile
From: ron minnich
Sent: Friday, September 30, 2022 9:00 AM
To: Nico Huber
Cc: Arthur Heymans ; coreboot
Subject: [coreboot] Re: FSP 2.4: runtime blobs!
note that I am having this exact same problem in the RISC-V community:
https://github.com/riscv-non
note that I am having this exact same problem in the RISC-V community:
https://github.com/riscv-non-isa/riscv-sbi-doc/issues/102
People just like their SMM. It's hard to kill.
I fear that you're not going to get much luck with Intel, which is why I
try to work with non-Intel CPUs as much as I ca
Hi Arthur, coreboot fellows,
On 30.09.22 13:53, Arthur Heymans wrote:
> What are your thoughts?
printing, bonfire...
> Do we take a stance against FSP-I integration in coreboot?
I think we already do. From coreboot.org:
"coreboot is an extended firmware platform that delivers a lightning
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