On Fri, Sep 15, 2017 at 7:40 PM, Fabian wrote:
> Hi everyone,
>
> I try to get coreboot run on my H8SCM. Sadly I get no log over serial or USB.
> So I want to give SPI console a try. It seems to be a very new feature
> introduced here [1].
Do you have a tested usbdebug
On 09/15/2017 12:40 PM, Fabian wrote:
Hi everyone,
I try to get coreboot run on my H8SCM. Sadly I get no log over serial or USB.
The H8SCM has serial ports that are routed via the winbond BMC chip
slash pseudo super I/O, I too have been unable to get output on it.
One more question to the
Hi Fabian,
It was ported to older intel architectures by Nicola Corna here :
https://review.coreboot.org/#/c/21107/
I don't know what would need to be done to port it to work with amd,
but in theory, all it needs is for the chipset to support SPI
operations. If it can read and write to the spi
Hi everyone,
I try to get coreboot run on my H8SCM. Sadly I get no log over serial or USB.
So I want to give SPI console a try. It seems to be a very new feature
introduced here [1].
When I compile coreboot it fails with this warning:
warning: (CPU_SPECIFIC_OPTIONS && CPU_SPECIFIC_OPTIONS &&
Hi everyone,
I mentioned this during my presentation at the coreboot conference
last week, and I was waiting for it to be merged before I announced it
on the mailing list.
For those of you working on recent hardware (this was tested on
skylake only, for broadwell to work, we need to add the spi
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