Von: Wolfgang Kamp - datakamp Gesendet: Freitag, 8. Mai 2015 09:34 An: 'Kyösti Mälkki' Betreff: AW: [coreboot] AGESA PI for Olivehill+
I have SPD EEPROM on board. File is checked. But I think required DDR3 seed values are different between memory down star topology and SODIMM DDR3 modules in fly by topology. But in binary Pi I see no way to change values. The only solution I see is to recompile AGESA and create a custom binary Pi. I can do this but is there anyone who has experience doing this way for coreboot? Regards, Wolfgang -----Ursprüngliche Nachricht----- Von: coreboot [mailto:coreboot-boun...@coreboot.org] Im Auftrag von Kyösti Mälkki Gesendet: Donnerstag, 7. Mai 2015 17:22 An: coreboot@coreboot.org Betreff: Re: [coreboot] AGESA PI for Olivehill+ On to, 2015-05-07 at 13:19 +0000, Wolfgang Kamp - datakamp wrote: > Hi Bruce, > > is it right that the AGESA Pi binary for AMD Olivehill+ board is not usable > for custom board implementations of FT3B GSOC? > For example, if we use memory down design in star topology, AGESA will fail > to initialize DDR3. > > Regards, > Wolfgang > I assume you have left out SPD eeproms from BOM, so have you already created and double-checked the SPD files? We have some boards in the tree doing that already. I hope to upstream DB-FT3b-LC board sources to coreboot.org, possibly next week. That may or may not help You further. Do you have PI build with raminit logging enabled? Regards, Kyösti -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
