On Fri, Jun 09, 2017 at 12:47:59PM +0800, 王翔 wrote:
> On Friday,June 9, 2017 at 12:34 PM,王翔 wrote:
[...]
> >I get source frome https://github.com/riscv/riscv-tools.git.
> >Compare the difference with https://github.com/riscv/riscv-isa-sim/pull/53
> >and fix the code.
> >The difference of Our pat
On Friday,June 9, 2017 at 12:34 PM,王翔 wrote:
>On Friday,June 9, 2017 9:17 AM, Jonathan Neuschäfer wrote:
>>On Thu, Jun 08, 2017 at 05:32:31PM +0800, 王翔 wrote:
>>> I try to debug coreboot with **spike**.
>>> I has apply the **8250 usart patch** to **spike**.
>>I haven't updated the patches at [1]
On Friday,June 9, 2017 9:17 AM, Jonathan Neuschäfer wrote:
>On Thu, Jun 08, 2017 at 05:32:31PM +0800, 王翔 wrote:
>> I try to debug coreboot with **spike**.
>> I has apply the **8250 usart patch** to **spike**.
>I haven't updated the patches at [1] in a while. Please check if the two
>patches in [
On Thu, Jun 08, 2017 at 05:32:31PM +0800, 王翔 wrote:
> I try to debug coreboot with **spike**.
> I has apply the **8250 usart patch** to **spike**.
I haven't updated the patches at [1] in a while. Please check if the two
patches in [2] work for you if you also apply the following patch to
coreboot
I try to debug coreboot with **spike**.
I has apply the **8250 usart patch** to **spike**.
But I get from the official website of the code can not pass the test.
I found some BUG when I debug this.
I want to submit the code but I can't test it. What can i do, who can help me.
I get code from `h
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