The PLL multiplier can have a max. value of 32 and
the PLLDIV2 can have a min value of 1. So depending on
your input oscillator, you shd be able to achieve
higher clock rate. For eg., 27Mhz Crystal * 31 / 1 =
800Mhz. This is the input to the DDR controller. The
output CLKO is half of that. So 40
The ECC generation on the DM644x happens in 512 byte chunks. So when using a
large block device, the page read or write happens four times, so you actually
generate four ECCs, each of which is stored in a 4-byte chunk of a 16-byte
chunk of the spare region. So after a complete page write opera
Hi,
I would like to know issues in using RNDIS mode with Davinci. I
want to avoid IRQ-per-packet and use RNDIS to transfer data. I am
going through cppi-dma.c form the davinci 2.6.20 git tree and I have
seen comments suggesting that CPPI-RX is working s expected and as of
now IRQ-per-packet is
Hi everybody,
I am writing USB host controller driver for the davinci .
TMS320DM6446 DMSoC Universal Serial Bus (USB) Controller.
I am connecting an external hub to the root hub port and when I try to
connect a USB mass storage and one USB mouse,
Mouse is giving some problem
Folks, please advise!
sprue22b "DDR2 Memory Controller" tells in table 1 on page 10 that
highest DDR2 clock freq is 162 MHz. Is it real maximum?
Is it correct that DDR2-400 works on non maximum of throughput and
there is no reason to use more faster (DDR2-800 for instanse) chips?
It is very str
To be precise, the cgtools are available with either 1) A CCS license where you
can download the cgtools from Update Advisor or 2) in the full DVSDK-L or
DVSDK-3L product.
The other components can be downloaded form DVEVM updates site.
From: [EMAIL PRO
Hi All,
We implemented the patch provided by Ivon Tonchev. But the problem still
persists. There is no change in the way we are getting the output.
Let me elaborate our problem and hardware a bit more.
We are using nand flash chip of STMicro-NAND01G-B2B.
And for DDR we use the chip Micro
I have access to this board:
http://www.lyrtech.com/DSP-development/dsp_fpga/sffsdrevaluationmodule.php
Unfortunately, Lyrtech only provides Integrity on the ARM. I would like
to get Linux running on this board. I am guessing, I need to start by
getting u-boot running. It looks like the board
Hi,
I am using DSPLINK in my multithreaded application.
>From DSPLINK I am using CHNL_Issue()/ CHNL_Reclaim() and
message MSGQ_Get ()/ MSGQ_Put () API to communicate with DSP.
I wanted to know is these Non-blocking APIs (CHNL_Reclaim() and MSGQ_Get
()) are interrupt driven.
You need to engage with that 3rd party and purchase the DVSDK-L. This
should include the Framework Components, DSP BIOS and the Linux code
generation tools. There is also a version of the DVSDK (DVSDK-3L) which
includes a license of Code Composer Studio.
Brandon Azbell
Texas Instruments
Sen
Thanks.But I don't have the
cg_setuplinux_6_0_3_02.bin,sp_bios_setuplinux_5_30_00_11.bin and
dvsdk_setuplinux_1_10_00_30.bin.I bought the EVM board from one of TI's 3rd
parties.They offer me 4 CDs,CD1 contains the
mvl_target_setuplinux_#_##_##_##.bin,I get the MontaVista target file system
afte
Hello,
When you install cg_setuplinux_6_0_3_02.bin you will get cgtools as: cg6x_6_0_3
Installing dsp_bios_setuplinux_5_30_00_11.bin you will get bios_5_30
Installing dvsdk_setuplinux_1_10_00_30.bin will give you frameworks components
These all bin files are provided in DVSDK kit.
Regards
Jiten
Hi,
I think you need full DVSDK ,and CCS3.2 .
Best regards
Andy.Lu
From: [EMAIL PROTECTED]
[mailto:[EMAIL PROTECTED] On Behalf Of
小小
Sent: April 27, 2007 4:33 PM
To: davinci-linux-open-source@linux.davincidsp.com
Subject: where to get the cgtools
Hello everybody! I'm a beginner of D
Hello everybody! I'm a beginner of Davinci,I can't find the
cgtools(C64P.rootDir),the BIOS(BIOS_INSTALL_DIR) and the
framework(FC_INSTALL_DIR) directory in the DVEVM_INSTALL_DIR .They are
necessary if I want to build a new or rebuild the demos programmes running on
the DSP side,aren't they?(Un
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