questions on DM6467

Hi All, Is it possible that I only use DM6467's DSP core for a PCI slave device? Thanks George ___ Davinci-linux-open-source mailing list Davinci-linux-open-source@linux.davincidsp.com

Re: questions on DM6467

Hi If I am not mistaken, pci is under arm control Albert On 6/12/08, Gu George [EMAIL PROTECTED] wrote: Hi All, Is it possible that I only use DM6467's DSP core for a PCI slave device? Thanks George ___ Davinci-linux-open-source mailing list

RE: About the cache issues of dm6446

6727 has ONLY L1P (i.e. there is no L1D and no L2). Its L1P is not configurable as SRAM. I'm not sure I understand your question about the single cache line. The cache always operates on cache lines, so yes, a single cache line can be a victim. How much does what take?

RE: What's on the target board?

Hi, I am not sure what you are asking for here (the bit before the numbered questions) I also assume you have a DM6446 not a DM355? 1/ The demo files are not installed on the NFS root filesystem. If you want them they are on one of the CDs or if you have a DM6446 they are in the /dev/hda2

Motion jpeg demo on code engine 2.10 does not working

Hello , Here is description of the problem: We are using eInfochip DVPB board with DM6446 ans software: -Monta Vista Linux - Codec Engine 2.10 - DSPLINK 1.50 - DSP/BIOS 5.32.01 We have downloaded application report SPRAAH9A “Motion JPEG Demo on TMS320DM6446” from

RE: About the cache issues of dm6446

1) If you're using projects from elsewhere then the default won't really matter, you'll need to look at how it was configured by the person that created the tcf file. 2) Use the BCACHE module from BIOS. From: kashin Lin [mailto:[EMAIL PROTECTED] Sent:

RE: cmem issure of DVEVM_1_30

Udev is there, it just looks different in the 2.6.23 kernel. CMEM v2.00.01 was written for the 2.6.10 kernel. Sometime between 2.6.10 and 2.6.23 the 'class_simple' interface was replaced by 'class'. Later CMEMs support both interfaces, dependant on: #if LINUX_VERSION_CODE =

Re: About the cache issues of dm6446

Hi everybody thanks for your anwers. Since there is no L1D cache on the 6727, there is no need to victimize a single cache line - what I meant is to force the cache to refresh a specific cache line and force it to refetch data from external memory. Are you sure that the 6727 has no L1D? and if so,

RE: About the cache issues of dm6446

Albert, This is off topic. Please post your question here in the floating point section: https://community.ti.com/forums/ Brad From: Albert Burbea [mailto:[EMAIL PROTECTED] Sent: Thursday, June 12, 2008 12:28 PM To: Griffis, Brad Cc: Andre