[PATCH] serial: 8250: Add cpufreq support

2012-04-03 Thread Shankarmurthy, Akshay
From: Chaithrika U S chaithr...@ti.com On DA850/OMAP-L138 SoC, the PLL which supplies the clock to CPU also feeds the UART and the UART input frequency can change when the CPU frequency is scaled. This patch adds cpufreq support for 8250 serial driver. A clk structure member has been added to

[PATCH 3/4] arm: davinci: use for_each_set_bit_from

2012-04-03 Thread Akinobu Mita
Use for_each_set_bit_from to iterate over all the set bit in a memory region. Signed-off-by: Akinobu Mita akinobu.m...@gmail.com Cc: Sekhar Nori nsek...@ti.com Cc: Kevin Hilman khil...@ti.com Cc: davinci-linux-open-source@linux.davincidsp.com Cc: Russell King li...@arm.linux.org.uk Cc:

Re: [PATCH] serial: 8250: Add cpufreq support

2012-04-03 Thread Alan Cox
This patch was submitted 2 years ago but didn't make it to the mainline. Now i am reposting it. Can you fix it instead of just reposting it ? +#ifdef CONFIG_CPU_FREQ +static int serial8250_cpufreq_transition(struct notifier_block *nb, + unsigned

[PATCH] arm: da850: change ASYNC/PLL0_SYSCLK3 clock rate with DVFS

2012-04-03 Thread Manjunathappa, Prakash
Clock for EMIF is derived from ASYNC clock domain(PLL0_SYSCLK3) and was configured with fixed divider as there was no significant performance degradation with existing NAND/NOR EMIF devices if it is not reconfigured accordingly at different OPPs. On systems where devices other than NAND/NOR are

Re: [PATCH] arm: da850: change ASYNC/PLL0_SYSCLK3 clock rate with DVFS

2012-04-03 Thread Michael Williamson
On 4/3/2012 9:01 AM, Manjunathappa, Prakash wrote: Clock for EMIF is derived from ASYNC clock domain(PLL0_SYSCLK3) and was configured with fixed divider as there was no significant performance degradation with existing NAND/NOR EMIF devices if it is not reconfigured accordingly at different