Hi,
has anyone ported Android2.2 on DM355?
Can anyone give me directions.
azam.
--
Happiness keeps you Sweet, Trials keep you Strong, Sorrows keep you Human,
Failures keep you humble , Success keeps You Glowing, but Only God
keeps You Going!
___
Davi
Dear INAGAKI and SUZUKI,
I used your patch for putting DM355 in deep sleep.
While going to deep sleep the code works fine. But when I try to wake up
DM355 it fails sometime,
wake-up fails randomly. Please can you suggest me what can be the problem.
I am using kernel version 2.6.10 and I added t
Hi Steve,
I was able to put PLL0 in bypass mode on DM355.
But I am unable to put PLL1 in bypass mode since PLL1 supplies clock to DDR
memory.
Can you please tell me how do I make DDR memory to use the internal clock
instead of PLL1 clock?
Is it possible to put PLL1 in bypass mode?
Thanks,
azam.
.
Thanks a lot for the help.
Thanks,
azam.
On Thu, Jul 23, 2009 at 5:36 PM, Steve Chen wrote:
> On Thu, 2009-07-23 at 15:41 +0530, Azam Ansari wrote:
> > Hi Steve,
> >
> > When I try to write PLLEN bit in PLLCTL register of PLL1 it crashes.
> >
> > But When I r
Hi Steve,
When I try to write PLLEN bit in PLLCTL register of PLL1 it crashes.
But When I read it works fine. Can you please suggest me how do I write the
pll registers?
Below is how I try to write PLL register.
pllcnt = davinci_readl(DAVINCI_PLL_CNTRL0_BASE + PLLCTL);
davinci_writel(DA
Hi All,
I have written following function to do pll bypass.
void davinci_clk_at24MHz(void)
{
struct clk *clkp;
static struct clk *board_clks;
int count = 0, num_clks;
unsigned long pllcnt;
if (cpu_is_davinci_dm355()) {
pllcnt = davinci_readl(DAVINCI_PLL_CNTRL0_BASE +
Hi All,
I am trying to put DM355 in Deep Sleep mode.
When I call the deep sleep function it gives me kernel dump while putting
MMC device in to deep sleep.
I don't know much about the MMC module. Does anyone know what can be the
reason.
Thanks,
azam.
Dear All,
I integrated the PM patch send by you with kernel version 2.6.10. But when I
do
$ echo mem > /sys/power/state
the kernel hangs.
Below is the kernel dump.
r...@192.168.0.104:/sys/power# echo mem > state
Stopping tasks: ==|
Unable to handle kernel NULL pointer dereference at
Hi Steve,
Where can I get the latest kernel version from? I check TI website but I
didn't find it.
Thanks,
Azam.
On Fri, Jul 10, 2009 at 3:52 AM, Steve Chen wrote:
> On Thu, 2009-07-09 at 21:00 +0530, Azam Ansari wrote:
>
> ...
>
> >
> > > constant
>
530, Azam Ansari wrote:
> > Hi Steve,
> >
> > I added the patch for Power Management in DM355. But during
> > compilation I get following error:
> >
> > arch/arm/mach-davinci/io.c:47: error: unknown field `pfn' specified in
> > initializer
> > arch/ar
Hi Steve,
I added the patch for Power Management in DM355. But during compilation I
get following error:
arch/arm/mach-davinci/io.c:47: error: unknown field `pfn' specified in
initializer
arch/arm/mach-davinci/io.c:47: warning: implicit declaration of function
`phys_to_pfn'
arch/arm/mach-davinci/
Hi All,
I added the patch for Power Management in DM355. But during compilation I
get following error:
arch/arm/mach-davinci/io.c:47: error: unknown field `pfn' specified in
initializer
arch/arm/mach-davinci/io.c:47: warning: implicit declaration of function
`phys_to_pfn'
arch/arm/mach-davinci/io
Hi All,
I added the patch for Power Management in DM355. But during compilation I
get following error:
arch/arm/mach-davinci/io.c:47: error: unknown field `pfn' specified in
initializer
arch/arm/mach-davinci/io.c:47: warning: implicit declaration of function
`phys_to_pfn'
arch/arm/mach-davinci/io
Hi Steve,
Does latest version support OSS with multiple codecs?
We are using OSS and we have already written lot of code for the codecs.
Thanks,
Azam.
On Thu, May 28, 2009 at 6:56 PM, Steve Chen wrote:
> On Thu, 2009-05-28 at 17:58 +0530, Azam Ansari wrote:
> > Hi,
> >
&
Hi,
I am using 2 different audio codecs. It seems that the davinci audio
supports only one codec at a time. How can I support more than one codec?
file: sound/oss/davinci-audio.c
int audio_register_codec(audio_state_t * codec_state)
{
int ret;
FN_IN;
/* We dont handle multiple codecs
Hi Steve,
Thanks for the help. I got the McBSP0 working for my audio chip.
Other than the changes you suggested I had to disable the internal clock of
McBSP0.
Thanks a lot for your help.
Best Regards,
Azam.
___
Davinci-linux-open-source mailing list
D
Hi All,
Does GIT kernel support DM355?
If it supports DM355 then where will I find all codes related to McBSP?
I downloaded the latest git kernel. When I do "make menuconfig" it gives
error as below:
Makefile:317: warning: overriding commands for target
`/home/azam/work/Linux'
Makefile:115: warni
at 7:45 AM, Liu Yebo wrote:
> Hi
> May be you should check below codes in file davinci-audio-dma-intfc.c.
> #define MCBSP_DXR (cpu_is_davinci_dm355() ? 0x01E04004 : 0x01E02004)
> #define MCBSP_DRR (cpu_is_davinci_dm355() ? 0x01E04000 : 0x01E02000)
>
> - Origin
>>>>
spin_unlock_irqrestore(&rrstlock, flags);
return;
}
If I dont get the frame sync then in that case what should I check?
Thanks,
Azam.
On Thu, Apr 30, 2009 at 5:02 AM, Steve Chen wrote:
> On Wed, 2009-04-29 at 23:57 +0530, Azam Ansari wrote:
> &g
Hi Steve,
>>Were you getting frame sync before the change?
No. I was not getting frame sync before the change either. Does it mean that
PINMUX setup is not correct?
Currently is set PINMUX3 = 0x3F.
>> and I noticed in function
>> audio_aic33_init in sound/oss/dm644x/davinci->> audio-aic33.c co
s(mcbsp[id].dma_tx_lch,
(unsigned long) (DAVINCI_MCBSP1_BASE + 4), 0,
0);
Please help...
On Mon, Apr 27, 2009 at 7:27 PM, Steve Chen wrote:
> On Mon, 2009-04-27 at 18:22 +0530, Azam Ansari wrote:
> > Hi Steve,
> >
> > When I check /proc
009-04-27 at 14:20 +0530, Azam Ansari wrote:
> > Hi,
> >
> > I have enabled McBSP0 in the board-dm355-evm.c file.
> > I have configure McBSP0 for audio but it is not working( Currently I
> > am using McBSP0 for only recording purpose...).
>
> May want to che
Hi,
I have enabled McBSP0 in the board-dm355-evm.c file.
I have configure McBSP0 for audio but it is not working( Currently I am
using McBSP0 for only recording purpose...).
I found that McBSP1 EDMA event is enable in mcbsp.c file by following code:
if (cpu_is_davinci_dm355()) {
__REG(EDM
Hi All,
I tried using the 8250 Uart driver on DM355 for communicating with the audio
codec but it seems that uart driver is heavily dependent on the tty driver.
I don't want to use the tty later as it makes the auido codec driver more
complex and difficult to maintain.
I just want to make followi
Hi All,
We are using UART1 to communicate with the Audio Codec. I checked
serial_core.c and 8250.c file for this. I didn't find anything that can be
directly used to communicate through UART1.
I was able to register the port using serial8250_register_port() function.
But how do I configure the po
Hi All,
I have got an issue when using GPIO6 for motion detection.
I am using GPIO6 for motion detection.
Whenever motion is detected interrupt is generated and IRQ handler is
called.
>From IRQ handler I just call tasklet_schedule()
below is code for IRQ:
static irqreturn_t vpfe_motion_isr(int
Hi,
Can we configure McBSP on DM355 to support PCM interface?
4 line interface:
PCMCLK
PCMSYNC
PCMI
PCMO
The PCM interface transmits and receives data at the PCMO and PCMI terminals
respectively. The data is
transmitted or received at the PCMCLK speed once every PCMSYN cycle.
If we can
Hi All,
Can we configure McBSP on DM355 to support PCM interface?
4 line interface:
PCMCLK
PCMSYNC
PCMI
PCMO
The PCM interface transmits and receives data at the PCMO and PCMI terminals
respectively. The data is
transmitted or received at the PCMCLK speed once every PCMSYN cycle.
If we ca
Hi All,
I need to configure McBSP for PCM interface.
Is it possible to configure McBSP for PCM interface?
If it is possible then please let me know how to configure McBSP?
-Azam
___
Davinci-linux-open-source mailing list
Davinci-linux-open-source@lin
on FSR PIN not CLKR PIN of DM355.
>
> - Original Message -
> *From:* Azam Ansari
> *To:* Liu Yebo
> *Cc:* Davinci-linux-open-source@linux.davincidsp.com
> *Sent:* Wednesday, March 04, 2009 5:15 PM
> *Subject:* Re: DM355 daughter sound card problem
>
> Hi Liu,
&g
Hi,
There is a interrupt line connected to GIO6 pin on DM355.
Whenever motion is detected the GIO6 pin is set High.
Below is what I have done to configure the GIO6 for interrupt.
ret = request_irq(IRQ_DM355_GPIO6, vpfe_motion_isr, SA_INTERRUPT,
"dm355v4l2", (void *)&vpfe_device);
Hi,
What is the Codec that you are using? Does it support line mixing?
Thanks.
On Mon, Mar 9, 2009 at 3:38 PM, Prabhu Kalyan Rout wrote:
> Hi,
> My requirement is to capture from both LINE IN and MIC. But current OSS
> functionality does not allow us to do that
> Can any body tell me how to ac
Hi Liu,
I am making driver for TechWell TW2835 chip. It is a audio/video mux.
2009/3/4 Liu Yebo
> Are you working with AIC33 on your daughter sound board ?
>
>
> - Original Message -
> *From:* Azam Ansari
> *To:* liuy...@covond.com ; Davinci-linux-open-source@li
al_config.pcr0 | SCLKME);
>
> SCLKME CLKSM Input Clock For Sample Rate Generator
> 0 0 Signal on CLKS pin
> 0 1 ASP internal input clock
> 1 0 Signal on CLKR pin
> 1 1 Signal on CLKX pin
>
> - Original Message ---
ME CLKSM Input Clock For Sample Rate Generator
> 0 0 Signal on CLKS pin
> 0 1 ASP internal input clock
> 1 0 Signal on CLKR pin
> 1 1 Signal on CLKX pin
>
>
>
> ----- Original Message -
> *From:* Azam Ansari
> *To:
Hi,
I missed to say about one more setting that I am using
#define MCBSP_DXR 0x01E02004
#define MCBSP_DRR 0x01E02000
2009/3/4 Azam Ansari
> Hi,
>
> I am sorry I didn't say this before. I am already using the setting
> suggested by you.
>
> Below is the detailed
MCBSP_DXR (cpu_is_davinci_dm355() ? 0x01E04004 :
> >> 0x01E02004)
> >> #define MCBSP_DRR (cpu_is_davinci_dm355() ? 0x01E04000 :
> >> 0x01E02000)
> >> like this
> >> #define MCBSP_DXR (cpu_is_davinci_dm355() ?
> >&
Please can you provide some more details
Which clock to configure?
How to configure the clock?
2009/3/3 Kapil Pendse
> Hi All,
>
>
> I am developing driver for daughter sound card on DM355 by modifying the
> AIC33 driver.
>
>
>
> I2C is working fine and the ioctl's are working fine but recor
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