On Mon, Aug 04, 2014 at 03:26:56PM +0300, Peter Ujfalusi wrote:
The edma_setup_from_hw() should know about the CC number when parsing the
CCCFG register - when it reads the register to be precise. The base
addresses for CCs stored in an array and we need to provide the correct id
to
On Thu, Jul 31, 2014 at 01:12:37PM +0300, Peter Ujfalusi wrote:
In case of edma_alloc_slot() failure during probe we should return the error
unchanged to make debugging easier.
Applied both
Thanks
--
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On Tue, Jul 08, 2014 at 01:46:35PM +0300, Peter Ujfalusi wrote:
Hi,
It is preferred that audio is served with the highest priority queue in order
to
avoid delays in data transfer between memory and audio IP.
The following series will add an API to arch code to assign a channel to a
On Wed, Jul 16, 2014 at 03:29:19PM +0300, Peter Ujfalusi wrote:
Hi,
After this series clients can ask to not receive notifications after each
period.
In this case we can disable the completion interrupt since the position
reporting
does not rely on it for cyclic mode.
Patchset for ASoC
On Thu, Apr 24, 2014 at 10:29:50AM +0300, Peter Ujfalusi wrote:
It helps to identify issues if we have some information regarding to the
channel which the event is associated.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
Acked-by: Joel Fernandes jo...@ti.com
Applied, thanks
--
On Thu, Apr 17, 2014 at 12:58:33AM -0500, Joel Fernandes wrote:
The vchan lock in edma_callback is acquired in hard interrupt context. As
interrupts are already disabled, there's no point in save/restoring interrupt
mask bit or cpsr flags.
Get rid of flags local variable and use spin_lock
On Mon, Apr 14, 2014 at 02:41:55PM +0300, Peter Ujfalusi wrote:
Hi,
Changes since v2:
- Dropped patch 10 from v2 (simplify direction configuration...)
- Dropped the channel priority related patches since we are going to go via
different route for configuring the priority.
- Added ACK
On Mon, Apr 14, 2014 at 02:42:04PM +0300, Peter Ujfalusi wrote:
It helps to identify issues if we have some information regarding to the
channel which the event is associated.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
Acked-by: Joel Fernandes jo...@ti.com
This failed to apply, cna
On Fri, Apr 18, 2014 at 09:50:33PM -0500, Joel Fernandes wrote:
We add DMA memcpy support to EDMA driver. Successful tests performed using
dmatest kernel module. Copy alignment is set to DMA_SLAVE_BUSWIDTH_4_BYTES and
users must ensure length is aligned so that copy is performed fully.
On Fri, Apr 18, 2014 at 11:34:50AM -0500, Joel Fernandes wrote:
On 04/18/2014 03:50 AM, Russell King - ARM Linux wrote:
On Thu, Apr 17, 2014 at 07:56:50PM -0500, Joel Fernandes wrote:
Free the vd (virt descriptor) after the callback is called. In EDMA driver
atleast which uses virt-dma, we
On Mon, Apr 14, 2014 at 02:01:11PM +0530, Sekhar Nori wrote:
Vinod,
On Wednesday 19 March 2014 11:25 AM, Sekhar Nori wrote:
The code to handle any length SG lists calls edma_resume()
even before edma_start() is called. This is incorrect
because edma_resume() enables edma events on the
On Fri, Apr 11, 2014 at 12:38:00PM +0300, Peter Ujfalusi wrote:
On 04/11/2014 11:56 AM, Sekhar Nori wrote:
On Friday 11 April 2014 02:20 PM, Peter Ujfalusi wrote:
On 04/11/2014 11:17 AM, Sekhar Nori wrote:
On Tuesday 01 April 2014 06:36 PM, Peter Ujfalusi wrote:
Use the EVENTQ_1 for
On Fri, Apr 11, 2014 at 02:32:28PM +0300, Peter Ujfalusi wrote:
Hi Vinod,
On 04/11/2014 12:42 PM, Vinod Koul wrote:
On Fri, Apr 11, 2014 at 12:38:00PM +0300, Peter Ujfalusi wrote:
On 04/11/2014 11:56 AM, Sekhar Nori wrote:
On Friday 11 April 2014 02:20 PM, Peter Ujfalusi wrote:
On 04
On Fri, Apr 11, 2014 at 03:23:54PM +0300, Peter Ujfalusi wrote:
On 04/11/2014 02:31 PM, Vinod Koul wrote:
I would say that it is channel based config. I don't see the reason why
would
one mix different priorities on a configured channel between descriptors.
If not then we can add
On Tue, Apr 01, 2014 at 04:06:04PM +0300, Peter Ujfalusi wrote:
Pause/Resume can be used by the audio stack when the stream is paused/resumed
The edma platform code has support for this and the legacy audio stack used
this.
Signed-off-by: Peter Ujfalusi peter.ujfal...@ti.com
---
On Thu, Apr 10, 2014 at 11:36:30AM -0500, Joel Fernandes wrote:
On 04/01/2014 08:06 AM, Peter Ujfalusi wrote:
To improve latency with cyclic DMA operation it is preferred to
use different eventq/tc than the default which is used by all
other drivers (mmc, spi, i2c, etc).
When preparing
On Tue, Apr 01, 2014 at 04:06:01PM +0300, Peter Ujfalusi wrote:
Hi,
This is basically a resend of the previous series:
https://lkml.org/lkml/2014/3/13/119
with removed ASoC patches (most of them are applied already).
Changes since v1:
- ASoC patches removed
- Comments from Andriy
On Mon, Mar 17, 2014 at 09:14:14AM -0400, Jon Ringle wrote:
On Mon, 17 Mar 2014, Sekhar Nori wrote:
Hi Jon,
On Monday 17 March 2014 06:28 PM, Jon Ringle wrote:
On Mon, 17 Mar 2014, Sekhar Nori wrote:
The code to handle any length SG lists calls edma_resume()
even before
On Fri, Nov 01, 2013 at 07:48:16PM +0800, Nicolin Chen wrote:
Since gen_pool_dma_alloc() is introduced, we implement it to simplify code.
Acked-by: Vinod Koul vinod.k...@intel.com
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On Thu, Oct 24, 2013 at 12:57:02PM -0500, Joel Fernandes wrote:
Rebased on slave-dma/next branch and reapplied:
Looks like your MUA caused lines to get wrapped and patch is corrupt, can you
pls resend again using git-send email. I tried even the patch from
patchworks but that too failed!
On Tue, Oct 22, 2013 at 10:30:43AM -0500, Joel Fernandes wrote:
On 10/21/2013 01:53 AM, Vinod Koul wrote:
On Mon, Sep 23, 2013 at 06:05:14PM -0500, Joel Fernandes wrote:
+ nr_periods = (buf_len / period_len) + 1;
?
consider the case of buf = period_len, above makes nr_period = 2
On Mon, Sep 23, 2013 at 06:05:14PM -0500, Joel Fernandes wrote:
@@ -449,6 +455,138 @@ static struct dma_async_tx_descriptor
*edma_prep_slave_sg(
return vchan_tx_prep(echan-vchan, edesc-vdesc, tx_flags);
}
+static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
+ struct
On Mon, Sep 23, 2013 at 06:05:15PM -0500, Joel Fernandes wrote:
davinci-pcm uses 16 as the no.of periods. With this, in EDMA we have to
allocate atleast 17 slots: 1 slot for channel, and 16 slots the periods.
Due to this, the MAX_NR_SG limitation causes problems, set it to 20 to make
cyclic
using 1 slot is managed by just DMA'ing 1 SG entry at a time.
much better series, thanks
I think i am okay with this, if anyone has objections pls speak up. Also
I need ack on the ARM patch 3/6 before I can carry this.
--
Vinod Koul
Intel Corp
On Thu, Aug 29, 2013 at 06:05:41PM -0500, Joel Fernandes wrote:
Process SG-elements in batches of MAX_NR_SG if they are greater
than MAX_NR_SG. Due to this, at any given time only those many
slots will be used in the given channel no matter how long the
scatter list is. We keep track of how
On Wed, Mar 06, 2013 at 02:56:05PM -0500, Matt Porter wrote:
Add a dmaengine API to retrieve slave SG transfer limits.
The API is optionally implemented by dmaengine drivers and when
unimplemented will return a NULL pointer. A client driver using
this API provides the required dma channel,
On Wed, Mar 06, 2013 at 02:56:04PM -0500, Matt Porter wrote:
Changes since v3:
- Change api name to dma_get_slave_sg_limits() to avoid
confusion with h/w caps which are static.
Changes since v2:
- Change to a separate slave sg specific api. Drop the
generic
t...@atomide.com
Acked-by: Arnd Bergmann a...@arndb.de
Acked-by: Vinod Koul vinod.k...@intel.com
---
include/linux/dmaengine.h | 16
1 file changed, 16 insertions(+)
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h
index bfcdecb..17d8ffd 100644
On Mon, Feb 04, 2013 at 02:47:02PM -0500, Matt Porter wrote:
Add a dmaengine API to retrieve slave SG transfer capabilities.
The API is optionally implemented by dmaengine drivers and when
unimplemented will return a NULL pointer. A client driver using
this API provides the required dma
On Mon, Jan 21, 2013 at 01:19:23PM -0500, Matt Porter wrote:
b) Sg segment length and numbers: Well these are capabilities, so it tells
you what is the maximum I can do. IMO it doesn't make sense to tie it down
to
burst, width etc. For that configuration you are checking maximum. What
On Thu, Jan 10, 2013 at 02:07:03PM -0500, Matt Porter wrote:
The call is implemented as follows:
struct dmaengine_chan_caps
*dma_get_channel_caps(struct dma_chan *chan,
enum dma_transfer_direction dir);
The dma transfer direction parameter may
On Thu, Jan 10, 2013 at 02:07:04PM -0500, Matt Porter wrote:
+/* struct dmaengine_chan_caps - expose capability of a channel
+ * Note: each channel can have same or different capabilities
+ *
+ * This primarily classifies capabilities into
+ * a) APIs/ops supported
+ * b) channel physical
On Thu, Jan 10, 2013 at 02:07:05PM -0500, Matt Porter wrote:
Implement device_channel_caps().
EDMA has a finite set of PaRAM slots available for linking
a multi-segment SG transfer. In order to prevent any one
channel from consuming all PaRAM slots to fulfill a large SG
transfer, the driver
On Sun, Jan 20, 2013 at 11:37:35AM -0500, Matt Porter wrote:
On Sun, Jan 20, 2013 at 12:37:34PM +, Vinod Koul wrote:
On Thu, Jan 10, 2013 at 02:07:03PM -0500, Matt Porter wrote:
The call is implemented as follows:
struct dmaengine_chan_caps
*dma_get_channel_caps(struct
On Sun, Jan 20, 2013 at 11:51:08AM -0500, Matt Porter wrote:
The explanation in the cover letter mentions that dmaengine_slave_config() is
required to be called prior to dmaengine_get_channel_caps(). If we
switch to the alternative API, then that would go away including the
dependency on
help in doing that.
--
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Intel Corp.
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the
dma_transaction_type enum be used directly along with dma_cap_mask_t?
Some of the capabilities above are not there in dma_caps_t like DMA_SG.
Also DMA_INTERRUPT and DMA_PRIVATE would not make much sense here.
BUT would help to keep things simpler if have one definition which
includes all.
--
Vinod Koul
On Mon, 2012-10-01 at 12:39 -0400, Matt Porter wrote:
Anything you can show at this point? ;) I'd be happy to drop the
half-hack
for a real API. If not, I'm going to carry that to v2 atm.
This is what I had done sometime back. Feel free to update
diff --git a/include/linux/dmaengine.h
On Fri, 2012-09-21 at 14:37 -0400, Matt Porter wrote:
On Fri, Sep 21, 2012 at 08:42:47AM -0700, Tony Lindgren wrote:
Can't we come up with a version of dma_request_slave_channel that works
both ways for now:
mcspi_dma-dma_rx =
dma_request_slave_channel_compat(mask,
On Fri, 2012-09-21 at 19:47 +0100, Russell King - ARM Linux wrote:
On Fri, Sep 21, 2012 at 10:45:29PM +0530, S, Venkatraman wrote:
On Thu, Sep 20, 2012 at 8:13 PM, Matt Porter mpor...@ti.com wrote:
The EDMA DMAC has a hardware limitation that prevents supporting
scatter gather lists with
care to send a
tested-by?
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Intel Corp.
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Please read the FAQ at http://www.tux.org/lkml/
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Intel Corp.
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http
be enabled for SPI. Care to send a patch
By 'this' you mean the Kconfig select? Then there should be no need of
a
new patch for this. It can be part of this patch itself, no?
Either way is okay for me.
--
~Vinod Koul
Intel Corp.
___
Davinci-linux
On Fri, 2012-08-31 at 22:32 +0530, Vinod Koul wrote:
On Fri, 2012-08-31 at 22:01 +0530, Sekhar Nori wrote:
Yes, this was the problem. Since the SPI driver now depends on
CONFIG_TI_EDMA for basic operation may be select CONFIG_TI_EDMA in
Kconfig if SPI is enabled? That should do until
On Tue, 2012-08-21 at 14:43 -0400, Matt Porter wrote:
Add a DMA engine driver for the TI EDMA controller. This driver
is implemented as a wrapper around the existing DaVinci private
DMA implementation. This approach allows for incremental conversion
of each peripheral driver to the DMA engine
On Tue, 2012-08-21 at 14:43 -0400, Matt Porter wrote:
Removes use of the DaVinci EDMA private DMA API and replaces
it with use of the DMA engine API.
Signed-off-by: Matt Porter mpor...@ti.com
---
+ struct dma_slave_config dma_rx_conf = {
+ .direction =
On Wed, 2012-08-22 at 12:04 -0400, Matt Porter wrote:
for querying of these types of limitations. Right now, the
mmc driver implicitly knows that EDMA needs this restriction
but it's something that should be queried before calling
prep_slave().
that's something we need to add; exporting
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