Hi Sekhar,
On Tue, Apr 10, 2012 at 00:35:57, Nori, Sekhar wrote:
> Hi Prakash,
>
> On 4/5/2012 2:43 PM, Manjunathappa, Prakash wrote:
> > Clock for EMIF is derived from ASYNC clock domain(PLL0_SYSCLK3) and was
> > configured with fixed divider as there was no significant performance
> > degradati
Hi Prakash,
On 4/5/2012 2:43 PM, Manjunathappa, Prakash wrote:
> Clock for EMIF is derived from ASYNC clock domain(PLL0_SYSCLK3) and was
> configured with fixed divider as there was no significant performance
> degradation with existing NAND/NOR EMIF devices if it is not
> reconfigured accordingly
Clock for EMIF is derived from ASYNC clock domain(PLL0_SYSCLK3) and was
configured with fixed divider as there was no significant performance
degradation with existing NAND/NOR EMIF devices if it is not
reconfigured accordingly at different OPPs.
On systems where devices other than NAND/NOR are in
