From: David Brownell <dbrown...@users.sourceforge.net>
Init the DM355 SPI0 device. Board init code would call this, which
would handle all pinmuxing needed.
This configures the second SPI interrupt for this controller; it's
not clear we'll actually want to use those controller IRQs ... but
the just-posted driver expects to have one. (Pure PIO doesn't need
them, it can poll; and DMA can be driven by EDMA irqs.) But it does
seem that at least on dm355 we'd want to avoid the first IRQ because
of irq mux conflicts with EDMA.
Signed-off-by: David Brownell <dbrown...@users.sourceforge.net>
---
arch/arm/mach-davinci/dm355.c | 58 +++++++++++++++++++++++++++
arch/arm/mach-davinci/include/mach/dm355.h | 5 ++
arch/arm/mach-davinci/psc.c | 7 ---
3 files changed, 63 insertions(+), 7 deletions(-)
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -11,6 +11,10 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+
+#include <linux/spi/spi.h>
#include <mach/dm355.h>
#include <mach/clock.h>
@@ -355,6 +359,60 @@ static struct clk *dm355_clks[] __initda
NULL,
};
+/*----------------------------------------------------------------------*/
+
+static u64 dm355_spi0_dma_mask = DMA_32BIT_MASK;
+
+static struct resource dm355_spi0_resources[] = {
+ {
+ .start = 0x01c66000,
+ .end = 0x01c667ff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IRQ_DM355_SPINT0_1,
+ .flags = IORESOURCE_IRQ,
+ },
+ /* Not yet used, so not included:
+ * IORESOURCE_IRQ:
+ * - IRQ_DM355_SPINT0_0
+ * IORESOURCE_DMA:
+ * - DAVINCI_DMA_SPI_SPIX
+ * - DAVINCI_DMA_SPI_SPIR
+ */
+};
+
+static struct platform_device dm355_spi0_device = {
+ .name = "spi_davinci",
+ .id = 0,
+ .dev = {
+ .dma_mask = &dm355_spi0_dma_mask,
+ .coherent_dma_mask = DMA_32BIT_MASK,
+ },
+ .num_resources = ARRAY_SIZE(dm355_spi0_resources),
+ .resource = dm355_spi0_resources,
+};
+
+void __init dm355_init_spi0(unsigned chipselect_mask,
+ struct spi_board_info *info, unsigned len)
+{
+ /* for now, assume we need MISO */
+ davinci_cfg_reg(DM355_SPI0_SDI);
+
+ /* not all slaves will be wired up */
+ if (chipselect_mask & BIT(0))
+ davinci_cfg_reg(DM355_SPI0_SDENA0);
+ if (chipselect_mask & BIT(1))
+ davinci_cfg_reg(DM355_SPI0_SDENA1);
+
+ spi_register_board_info(info, len);
+
+ davinci_clk_associate(&dm355_spi0_device.dev, "spi", "SPICLK");
+ platform_device_register(&dm355_spi0_device);
+}
+
+/*----------------------------------------------------------------------*/
+
void __init dm355_init(void)
{
davinci_clk_init(dm355_clks);
--- a/arch/arm/mach-davinci/include/mach/dm355.h
+++ b/arch/arm/mach-davinci/include/mach/dm355.h
@@ -15,4 +15,9 @@
void __init dm355_init(void);
+struct spi_board_info;
+
+void dm355_init_spi0(unsigned chipselect_mask,
+ struct spi_board_info *info, unsigned len);
+
#endif /* __ASM_ARCH_DM355_H */
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -103,13 +103,6 @@ static void dm355_psc_mux(unsigned int i
tmp &= ~(BIT(1) | BIT(0));
__raw_writel(tmp, base + DM355_EDMA_EVTMUX);
break;
- case DAVINCI_LPSC_SPI: /* SPI0 */
- /* expose SPI0_SDI
- * NOTE: SPIO_SDENA0 and/or SPIO_SDENA1
- * will need to be set too.
- */
- davinci_cfg_reg(DM355_SPI0_SDI);
- break;
}
}
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