I'm trying this again as I had a report the first try was garbled.
When I set up the controller (in DVFlasher) with these numbers, attempts
to flash lead to flash/RAM verification failures. I really think I am
doing the math OK, but I could be missing something (like an off by two)
I think I set the SYSCLOCK to 324 MHz, which should clock the DDR
interface at 162 Mhz and calculated the timing accordingly.
The numbers here work mostly, unless you memory test large sections of
RAM with u-boot:
http://trac.geekisp.com/opensdr/browser/HW_tools/sff_sdr/serial_loader/trunk/DVFlasher/ubl/src/dm644x.c#L29
Updating to these numbers leads to the problem described above.
// For Micron MT47H32M16BN-3 @ 324 MHz
const Uint8 DDR_NM = 0;
const Uint8 DDR_CL = 3;
const Uint8 DDR_IBANK = 2;
const Uint8 DDR_PAGESIZE = 2;
const Uint8 DDR_T_RFC = 17;
const Uint8 DDR_T_RP = 2;
const Uint8 DDR_T_RCD = 2;
const Uint8 DDR_T_WR = 2;
const Uint8 DDR_T_RAS = 6;
const Uint8 DDR_T_RC = 8;
const Uint8 DDR_T_RRD = 1;
const Uint8 DDR_T_WTR = 1;
const Uint8 DDR_T_XSNR = 18;
const Uint8 DDR_T_XSRD = 199;
const Uint8 DDR_T_RTP = 1;
const Uint8 DDR_T_CKE = 2;
const Uint16 DDR_RR = 1263;
const Uint8 DDR_Board_Delay = 3;
const Uint8 DDR_READ_Latency = 5;
const Uint32 PLL2_Mult = 24;
const Uint32 PLL2_Div1 = 12;
const Uint32 PLL2_Div2 = 1;
// Set CPU clocks
const Uint32 PLL1_Mult = 22; // DSP=594 MHz ARM=297 MHz
Can anyone see what I am doing wrong?
Philip
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