Hi,
I am working on a DM365 based customize board which has two nand chips
each of 1GB. At the UBoot level I am getting following errors:
*UBoot Log:*
**
U-Boot 2009.03 (Mar 18 2010 - 20:23:55)
I2C: ready
DRAM: 128 MB
NAND: NAND device: Manufacturer ID: 0x2c, Chip ID: 0xd3 (Micron
Krunal Patil wrote:
> I am working on a DM365 based customize board which has two nand
> chips each of 1GB. At the UBoot level I am getting following errors:
>
> UBoot Log:
>
> U-Boot 2009.03 (Mar 18 2010 - 20:23:55)
>
> I2C: ready
> DRAM: 128 MB
> NAND: NAND device: Manufacturer ID: 0
Hi Jon,
Thanks for the prompt response.
1. How can I verify whether UBoot is detecting and accessing both the
NANDs not only one?
2. Can you please through some light on "I would be more concerned
about the ECC errors and that the kernel is reporting BBT not found."
3. How can I
Krunal Patil wrote:
> 1.How can I verify whether UBoot is detecting and accessing both the
> NANDs not only one?
u-boot can read, write and erase NAND; you could erase and write a page on one
chip and see if it shows up on the other.
> 2.Can you please through some light on "I would be m
lt; davinci - linux -open-source@ linux . davincidsp .com>
Sent: Friday, June 11, 2010 3:13:54 PM
Subject: RE: DM365 UBoot + NAND Query
Krunal Patil wrote:
> 1. How can I verify whether UBoot is detecting and accessing both the
> NANDs not only one?
u-boot can read, write and erase NAND
patil"
Cc: "Davinci List"
Sent: Friday, June 11, 2010 3:13:54 PM
Subject: RE: DM365 UBoot + NAND Query
Krunal Patil wrote:
> 1.How can I verify whether UBoot is detecting and accessing both the
> NANDs not only one?
u-boot can read, write and erase NAND; you could era
?
Regards,
Krunal
- Original Message -
From: "Steve Poulsen"
To: davinci-linux-open-source@linux.davincidsp.com
Sent: Friday, June 11, 2010 8:53:35 PM
Subject: Re: DM365 UBoot + NAND Query
Krunal,
What version kernel are you using? One thing to note is that t
: "Steve Poulsen"
To: davinci-linux-open-source@linux.davincidsp.com
Sent: Friday, June 11, 2010 8:53:35 PM
Subject: Re: DM365 UBoot + NAND Query
Krunal,
What version kernel are you using? One thing to note is that the Chip
ID of 0xd3 can actually correspond to several layouts of the N
Original Message -----
From: "Steve Poulsen"
To: davinci-linux-open-source@linux.davincidsp.com
Sent: Friday, June 11, 2010 8:53:35 PM
Subject: Re: DM365 UBoot + NAND Query
Krunal,
What version kernel are you using? One thing to note is that the
Chip ID of 0xd3 can actually correspond to
Krunal Patil wrote:
> NAND device: Manufacturer ID: 0x2c, Chip ID: 0xd3 (Micron NAND 1GiB
> 3,3V 8-bit) 2 NAND chips detected
> Creating 5 MTD partitions on "nand_davinci.0":
> 0x-0x0078 : "bootloader"
> 0x0078-0x0080 : "params"
> 0x0080-0x00c0 : "kernel"
> 0x00c0-0x
t any
problem. Have you ever experienced this?
Regards,
Krunal
- Original Message -
From: "Steve Poulsen"
To: davinci-linux-open-source@linux.davincidsp.com
Sent: Friday, June 11, 2010 8:53:35 PM
Subject: Re: DM365 UBoot + NAND Query
Krunal,
What version kernel are you usin
Steve Poulsen wrote:
> 1) Use hexdump to view the first bit of the bootloader and note the
> data values. 2) Load a filesystem into filesystem2.
> 3) Use hexdump to view the first bit of the bootloader and note the
> changes. 4) hexdump filesystem2 and search for the pattern. ( you
> might dump it
Thanks for the valuable suggestions guys. Appreciate all your inputs. I
will be trying this today.
--
Regards,
Krunal
On 06/18/2010 03:20 AM, Jon Povey wrote:
Steve Poulsen wrote:
1) Use hexdump to view the first bit of the bootloader and note the
data values. 2) Load a filesystem into fi
Hi,
I tried using second approach but I am not able to access 2nd nand chip
from the UBoot. When I execute command "nand dump 0x4000" from the
Uboot I am getting error "Error (-22) reading page 4000". It works
well till address 0x3fff (1GB).
--
Regards,
Krunal
On 06/18/2010 03
Hi Guys,
Thnaks for the support. I have solved this issue. The problem was in the
FPGA logic which was enabling/disabling the CE0/1 signals for NAND
devices. Ideally for NAND-1 CE0 and NAND-2 CE1 should be high which was
swapped in my FPGA code. I concluded this by probing the CE0/1 signals
o
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