When interfacing FPGA to the DM6446 EVM EMIF do I need a bus switch on
CS3 for my device or is this handled already by the CPLD (Altera MaxII)?
Am I right in thinking simply accessing an address in the CS3 space
will automatically assert the CS3 signal?
I plan on only having 8 bits exposed, so can I leave the address lines
unconnected? That way any address I read within CS3 space will yield
the same result?
Thanks!
Nick
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