Hello Mr.Zhang
I am dealing with a similar application scenario with you.
Our ITE HDMI Rx will feed I2S stereo audio data and master wclk and bclk to
the McAsp2 of DM8148.
By default, McAsp is worling on DSP_B mode, which will consider every bit
clocked by bclk as validated data , however HDMI wi
of SRCTL4 0x190 = 0
value of SRCTL5 0x194 = 0
value of RFIFOCTL 0x1008 = 10404
value of RFIFOSTS 0x100c = 40
henry
--- On Thu, 3/24/11, Rao, Dipa wrote:
> From: Rao, Dipa
> Subject: RE: davinci-mcasp.c for TI816x
> To: "hong zhang" ,
> "davinci-linux-open-so
Thu, 3/24/11, Rao, Dipa wrote:
> From: Rao, Dipa
> Subject: RE: davinci-mcasp.c for TI816x
> To: "hong zhang" ,
> "davinci-linux-open-source@linux.davincidsp.com"
>
> Date: Thursday, March 24, 2011, 7:31 PM
> Can you send me the DMA programming
> being
,
.rxnumevt = 1,
};
---henry
--- On Thu, 3/24/11, Rao, Dipa wrote:
> From: Rao, Dipa
> Subject: RE: davinci-mcasp.c for TI816x
> To: "hong zhang" ,
> "davinci-linux-open-source@linux.davincidsp.com"
>
> Date: Thursday, March 24, 2011, 7:31 PM
-source@linux.davincidsp.com
Subject: Re: davinci-mcasp.c for TI816x
Dipa,
RINTCTL is not enbaled because AIC3X does not enable it.
External clock and rate:
AHCLKR = 12.287MHz
ACLKR = 3.072MHz
FSR = 48KHz
Following McASP register dumps on receive side.
value of PFUNC = 0
value of PDIR = 1
value
ang
> Subject: davinci-mcasp.c for TI816x
> To: davinci-linux-open-source@linux.davincidsp.com
> Date: Thursday, March 24, 2011, 4:55 PM
> List,
>
> I am doing hdmi SiI9135 for McASP receive side and make
> good progress. 64 words data are seen in receive FIFO. DMA
> does not deli
List,
I am doing hdmi SiI9135 for McASP receive side and make good progress. 64 words
data are seen in receive FIFO. DMA does not deliver them. Value of register
RFIFOSTS is 0x40 (64). But receive status register RSTAT value is 177.
Here is my question,
How to ignore error of RSYNCERR (Unexpe
