https://github.com/yellowback/ubuntu-precise-armadaxp/, but I haven't
checked in detail. If you're interested, I can probably dig the LSP
patch that does that.
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
--
To
2C is
working.
All in mainline, completely Device Tree based.
So isn't this entire discussion completely moot? The mainline support
for sunxi has already started since 6 months or so, and has been Device
Tree based from day one.
Best regards,
Thomas
--
Thomas Petazzoni, Free Electrons
Ker
ere is already a pinctrl driver for sunxi platforms (i.e Allwinner
SoCs), it's at drivers/pinctrl/pinctrl-sunxi.c, and it's DT-based and
allows to describe the pin muxing in the Device Tree.
Cc'ing Maxime Ripard, who is the mach-sunxi maintainer in the mainline
kernel.
Best regards,
uot; tells you... Which by itself is a very good indicator that
you're probably not the best interlocutor for Allwinner as far as
mainline development is concerned.
Best regards,
Thomas Petazzoni
--
Thomas Petazzoni, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, cons
;
};
So it means that MPP 4, 5, 20, 21, 22 and 23 will no longer be muxed as
sata0/sata1. Is this really what you want?
Best regards,
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
for SATA on this board.
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
Hello,
On Mon, 20 Feb 2017 17:22:38 +, Ben Hutchings wrote:
> You mean, define additional pinmux nodes and override the pinctrl-0
> property of &sata? More like this:
Yes, exactly.
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
h
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