it always says something like this:
PMD: tap1234: ioctl(35092) failed with error: No such device
PMD: Add queue to TAP tap1234 for qid 0
PMD: tap1234: ioctl(35108) failed with error: Cannot assign requested
address
PMD: tun_alloc(tap1234, 0) failed
PMD: tap1234: ioctl(35092) failed with error: No
Hi Jianfeng,
On Wed, Jun 21, 2017 at 07:30:08AM +0800, Tan, Jianfeng wrote:
> Hi Jiayu,
>
>
> On 6/20/2017 11:22 AM, Jiayu Hu wrote:
> > Hi Jianfeng,
> >
> > On Mon, Jun 19, 2017 at 11:43:20PM +0800, Tan, Jianfeng wrote:
> > >
> > > On 6/18/2017 3:21 PM, Jiayu Hu wrote:
> > > > In this patch,
On Mon, Jun 19, 2017 at 11:43:20PM +0800, Tan, Jianfeng wrote:
>
>
> On 6/18/2017 3:21 PM, Jiayu Hu wrote:
> >
> > Each element in the flow array records the information of one flow,
> > which includes two parts:
> > - key: the criteria of the same flow. If packets have the same key
> > val
These adapters support 100G link speed but the speed_capa bitmask in the
device info did not reflect that.
Signed-off-by: Martin Weiser
---
drivers/net/cxgbe/cxgbe_ethdev.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/net/cxgbe/cxgbe_ethdev.c b/drivers/net/cxg
These adapters support 100G link speed but the speed_capa bitmask in the
device info did not reflect that.
Signed-off-by: Martin Weiser
---
drivers/net/cxgbe/cxgbe_ethdev.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/net/cxgbe/cxgbe_ethdev.c b/drivers/net/cxg
On Wed, Jun 21, 2017 at 8:22 AM, Sam wrote:
> Thank you~
>
> 1. We have a compare test on qemu-kvm enviroment with huge page and without
> huge page. Qemu start process is much longer in huge page enviromwnt. And I
> write an email titled with '[DPDK-memory] how qemu waste such long time
> under
I think the series patches does not cover all area which need to adapt to u32
PCI domain,
We still need some other work to do:
we need define another macro such as PCI_PRI_FMT. Something like:
#define PCI_XXX_PRI_FMT "%.5" PRIx32 ":%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8
PCI_PRI_STR_SIZE also need to
After adding a fdir rule for IPv6 with input set TC, IPv6 packets
with the specific TC can't be assigned the right queue.
The root cause is that TC is parsed wrongly, this patch fixes
TC parsing problem.
Fixes: 7d83c152a207 ("net/i40e: parse flow director filter")
Cc: sta...@dpdk.org
Signed-off-b
> From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Martin Weiser
> Sent: Thursday, June 22, 2017 9:58 AM
> To: rahul.lakkire...@chelsio.com
> Cc: dev@dpdk.org; Martin Weiser
> Subject: [dpdk-dev] [PATCH v2] cxgbe: report 100G link speed capability for
> Chelsio T6
> adapters
>
> These adapte
Hi Jiayu,
> -Original Message-
> From: Hu, Jiayu
> Sent: Thursday, June 22, 2017 4:18 PM
> To: Tan, Jianfeng
> Cc: dev@dpdk.org; Ananyev, Konstantin; y...@fridaylinux.org; Wiles, Keith;
> Bie, Tiwei; Yao, Lei A
> Subject: Re: [PATCH v5 2/3] lib/gro: add TCP/IPv4 GRO support
>
> On Mon, Ju
Hi Ilia,
> -Original Message-
> From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of ilia.kura...@intel.com
> Sent: Monday, June 19, 2017 6:18 PM
> To: dev@dpdk.org
> Cc: Kurakin, Ilia
> Subject: [dpdk-dev] [PATCH] ether: add support for vtune task tracing
>
> From: Ilia Kurakin
>
> Th
Hi Nelio,
On 6/21/2017 2:02 PM, Nélio Laranjeiro wrote:
> On Wed, Jun 21, 2017 at 11:55:58AM +, Shachar Beiser wrote:
>> Missing room in flow allocation to store the drop specification.
>> Changing flow without storing the change in rte_flow.
>> Fixes: 88c77dedfbb0 ("net/mlx5: implement drop a
>> From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Martin Weiser
>> Sent: Thursday, June 22, 2017 9:58 AM
>> To: rahul.lakkire...@chelsio.com
>> Cc: dev@dpdk.org; Martin Weiser
>> Subject: [dpdk-dev] [PATCH v2] cxgbe: report 100G link speed capability for
>> Chelsio T6
>> adapters
>>
>> Thes
These adapters support 100G link speed but the speed_capa bitmask in the
device info did not reflect that.
Signed-off-by: Martin Weiser
---
drivers/net/cxgbe/cxgbe_ethdev.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/net/cxgbe/cxgbe_ethdev.c b/drivers/net/cxgbe/cxgbe_ethdev.c
> -Original Message-
> From: Trahe, Fiona
> Sent: Wednesday, June 21, 2017 6:40 PM
> To: De Lara Guarch, Pablo ; Doherty, Declan
>
> Cc: dev@dpdk.org; De Lara Guarch, Pablo ;
> sta...@dpdk.org; Trahe, Fiona
> Subject: RE: [dpdk-dev] [PATCH 2/9] test/crypto: fix wrong AAD setting
>
> Hi
On 6/21/2017 12:55 PM, Shachar Beiser wrote:
> Missing room in flow allocation to store the drop specification.
> Changing flow without storing the change in rte_flow.
> Fixes: 88c77dedfbb0 ("net/mlx5: implement drop action in hardware classifier")
>
> Signed-off-by: Shachar Beiser
> ---
> drive
From: Luca Boccassi
Commit 44a718c457b added rte_eth_tx_done_cleanup but it wasn't added
to the rte_ether_version.map so it cannot be used by applications
linking to shared libraries.
pktgen uses it since commit 44a718c457b
Fixes: 44a718c457 ("ethdev: add API to free consumed buffers in Tx ring"
On 21/06/2017 6:07 AM, Pablo de Lara wrote:
Socket id parsed from the user was checked
if it was in the range of available sockets.
This check is unnecessary, as the socket specified
might not have memory anyway, so it will fail
at memory allocation.
Therefore, the best solution is to remove thi
On 6/22/2017 4:07 AM, Chen, Jing D wrote:
>
>
>> -Original Message-
>> From: Wang, Xiao W
>> Sent: Thursday, June 22, 2017 7:20 PM
>> To: Chen, Jing D
>> Cc: dev@dpdk.org; sta...@dpdk.org; Wang, Xiao W
>> Subject: [PATCH v2] net/fm10k: initialize link status in device start
>>
>> Fm10k
On 21/06/2017 6:07 AM, Pablo de Lara wrote:
Socket id parsed from the user was checked
if it was in the range of available sockets.
This check is unnecessary, as the socket specified
might not have memory anyway, so it will fail
at memory allocation.
Therefore, the best solution is to remove thi
On 21/06/2017 6:07 AM, Pablo de Lara wrote:
Socket id parsed from the user was checked
if it was in the range of available sockets.
This check is unnecessary, as the socket specified
might not have memory anyway, so it will fail
at memory allocation.
Therefore, the best solution is to remove thi
On 21/06/2017 6:07 AM, Pablo de Lara wrote:
When creating a virtual pmd to test link bonding,
the socket id was checked, if it was in the range
of available sockets.
This check is unnecessary, as the socket specified
might not have memory anyway, so it will fail
at memory allocation.
Therefore,
From: Luca Boccassi
Commit 44a718c457b5 added rte_eth_tx_done_cleanup but it wasn't added
to the rte_ether_version.map so it cannot be used by applications
linking to shared libraries.
pktgen uses it since version 3.2.0.
Added to the 17.05 list as requested by Ferruh in case backporting is
needed
Hi Konstantin,
Adding Dmitry to this thread
Ilia
-Original Message-
From: Ananyev, Konstantin
Sent: Thursday, June 22, 2017 12:42 PM
To: Kurakin, Ilia ; dev@dpdk.org
Cc: Kurakin, Ilia
Subject: RE: [dpdk-dev] [PATCH] ether: add support for vtune task tracing
Hi Ilia,
> -Original M
Provide unique user data pointer in the extension calls for
each port.
Signed-off-by: John Miller
---
drivers/net/ark/ark_ethdev.c | 71 +---
drivers/net/ark/ark_ext.h| 4 +++
drivers/net/ark/ark_global.h | 5 ++--
3 files changed, 60 insertions(+),
Repairs a bug in the stats_reset where the wrong queue was
being passed into tx reset.
Signed-off-by: John Miller
---
drivers/net/ark/ark_ethdev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ark/ark_ethdev.c b/drivers/net/ark/ark_ethdev.c
index 55e6b24..fff2d8
On 6/8/2017 3:38 PM, Olivier Matz wrote:
Hi Hemant,
On Tue, 23 May 2017 15:03:48 +0530, Hemant Agrawal
wrote:
Debug logs are helpful for better debugging. Alloc
was having the logs, but logs were not present in free routines.
This patch add support for debug mode logs in free routine.
Also,
In case the alloc api is not able to allocate the required
number of buffer, it can return '0', which will not indicate
the failure to the calling function.
This patch fix the return value to indicate the failure.
Fixes: 5dc43d22b5ad ("mempool/dpaa2: add hardware offloaded mempool")
CC: sta...@dpd
The dpaa2_bp_list is being allocated using "rte_malloc",
but the free is done using "free". Fixing it to use
"rte_free".
Fixes: 5dc43d22b5ad ("mempool/dpaa2: add hardware offloaded mempool")
CC: sta...@dpdk.org
Signed-off-by: Hemant Agrawal
---
drivers/mempool/dpaa2/dpaa2_hw_mempool.c | 2 +-
1
Hi all,
I'm doing an unexpected stable release, which is expected to be released
in about two months. The reason I'm doing it is there is an import bug
fix commit that is needed for OVS 2.8 release. The fix is a vhost-user
commit comes from me. Well, unfortunately, I'm also the author of the
origi
Hi Jianfeng,
On Thu, Jun 22, 2017 at 05:35:23PM +0800, Tan, Jianfeng wrote:
> Hi Jiayu,
>
> > -Original Message-
> > From: Hu, Jiayu
> > Sent: Thursday, June 22, 2017 4:18 PM
> > To: Tan, Jianfeng
> > Cc: dev@dpdk.org; Ananyev, Konstantin; y...@fridaylinux.org; Wiles, Keith;
> > Bie, Tiwe
This patch series address some of the issues identified during testing on
latest code.
Last patch adds the support for multi-segment frames.
Hemant Agrawal (9):
net/dpaa2: set the eth driver from dpaa2 driver
net/dpaa2: set data align option in mc firmware
net/dpaa2: align the queue numbers
Signed-off-by: Hemant Agrawal
---
drivers/net/dpaa2/dpaa2_ethdev.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c
index da309ac..df11204 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.c
+++ b/drivers/net/dpaa
Configuring the MC FW to configure data alignment by default.
This help in improving performance for some of the platform variants.
Signed-off-by: Hemant Agrawal
---
drivers/net/dpaa2/base/dpaa2_hw_dpni.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/net/dpaa
Align dpaa2 pmd driver code to the way MC Firmware manages queues.
Signed-off-by: Hemant Agrawal
---
drivers/net/dpaa2/dpaa2_ethdev.c | 40
drivers/net/dpaa2/dpaa2_ethdev.h | 1 -
2 files changed, 16 insertions(+), 25 deletions(-)
diff --git a/drivers/n
Instead of qbman version, check the soc version for stashing
enablement decision
Signed-off-by: Hemant Agrawal
---
drivers/net/dpaa2/dpaa2_ethdev.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c
index
changing the nxp dpdk helper repository from helper to extras
Signed-off-by: Hemant Agrawal
---
doc/guides/nics/dpaa2.rst | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/doc/guides/nics/dpaa2.rst b/doc/guides/nics/dpaa2.rst
index 1ca27d4..6965121 100644
--- a/doc/guides
Making it off by default.
Signed-off-by: Hemant Agrawal
---
drivers/net/dpaa2/dpaa2_ethdev.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c
index 767eb9b..a1ef1cb 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.c
+++ b/driver
correct the while condition for cleanup in case of failure.
Fixes: a0d5c9caf0f1 ("bus/fslmc: add frame queue based dq storage")
Cc: sta...@dpdk.org
Signed-off-by: Hemant Agrawal
---
drivers/bus/fslmc/portal/dpaa2_hw_dpio.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/dr
From: Shreyansh Jain
Cleanup the dma map logic for memsegs. Earlier, in case
DMA mapping reaching end of segment, it reports a suprious error.
Signed-off-by: Shreyansh Jain
---
drivers/bus/fslmc/fslmc_vfio.c | 25 +
1 file changed, 17 insertions(+), 8 deletions(-)
diff
Change from byte based to frame based.
Signed-off-by: Hemant Agrawal
---
drivers/net/dpaa2/dpaa2_ethdev.c | 3 +--
drivers/net/dpaa2/dpaa2_ethdev.h | 9 -
2 files changed, 5 insertions(+), 7 deletions(-)
diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c
in
Signed-off-by: Hemant Agrawal
---
drivers/bus/fslmc/portal/dpaa2_hw_pvt.h | 27 -
drivers/net/dpaa2/dpaa2_rxtx.c | 189 ++--
2 files changed, 206 insertions(+), 10 deletions(-)
diff --git a/drivers/bus/fslmc/portal/dpaa2_hw_pvt.h
b/drivers/bus/fslmc/por
From: Luca Boccassi
Depending on the environment, make might echo the command being ran.
In mk/rte.sdkdoc.mk make is used to print the DPDK version to be
piped to doxygen. This causes the following to be written:
DPDK
/usr/bin/make-f/build/dpdk-jYjqnr/dpdk-16.11.2/mk/rte.sdkconfig.mkshowversion
From: Luca Boccassi
In the past couple of years a concerted effort among almost all Linux
distros has been striving toward achieving reproducible builds. [1]
This involves changes to the toolchain, new tools and CI systems. [2]
This first series fixes unreproducibility problems in DPDK with
rega
From: Luca Boccassi
The --exclude parameter must be passed before the input directory to
tar, otherwise it's silently ignored and the .doctrees directory is
installed by make install-doc.
Signed-off-by: Luca Boccassi
---
mk/rte.sdkinstall.mk | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-
From: Luca Boccassi
The result of find might not be stable depending on external
conditions.
Pipe it through LC_ALL=C sort to ensure reproducible results when
generating examples.dox.
Signed-off-by: Luca Boccassi
---
mk/rte.sdkdoc.mk | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Luca Boccassi
The output of wildcard might not be stable and depend on the
filesystem and other factors.
This means the content libdpdk.so linker script might change between
builds from the same sources.
Run the list through sort to ensure reproducibility.
Signed-off-by: Luca Boccassi
---
Hello,
I believe commit 260aae9a [1] has introduced a regression for the case
of 32-bit process running on a 64-bit kernel.
The commit is effectively casting mbuf->buf_physaddr to uintptr_t
before dereferencing it. It truncates the physical address to the width
of the process's uint, and in the t
Just fyi, the summary line should be lowercase apart from acronyms (DPDK
guidelines).
On 11/05/2017 02:56, Tonghao Zhang wrote:
The NUMA node information for PCI devices provided through
sysfs is invalid for AMD Opteron(TM) Processor 62xx and 63xx
on Red Hat Enterprise Linux 6, and VMs on some
> Pablo de Lara (4):
> cryptodev: remove socket id check
> crypto/scheduler: remove socket id check
> net/bonding: remove socket id check
> test/bonding: remove socket id check
Applied, thanks
On Thu, 22 Jun 2017 09:28:31 +
"Chang, Cunyin" wrote:
> I think the series patches does not cover all area which need to adapt to u32
> PCI domain,
> We still need some other work to do:
> we need define another macro such as PCI_PRI_FMT. Something like:
> #define PCI_XXX_PRI_FMT "%.5" PRIx3
Hello all,
I am observing Tx side packet drop when using a simple DPDK application in a
VM. The drop is not seen
when a delay in Clock-Cycles in applied. Is this an expected behavior?
Here is a test result:
Traffic Generator: Ostinato:
Ostinato:
Tx: 7.4 mbps
Rx: 7.3 mbps
Drop(DPDK TX): 22
> > From: Dahir Osman
> >
> > The rte_ip_frag_table_destroy procedure simply releases the memory for the
> > table without freeing the packet buffers that may be referenced in the hash
> > table for in-flight or incomplete packet reassembly operations. To prevent
> > leaked mbufs go through the
The PCI address consists of domain, bus, device, function.
The domain value is limited to 16 bits when received from ACPI,
but on virtual environments the host may use the full 32 bits to
distinguish direct hardware from synthetic buses.
Stephen Hemminger (3):
pci: remove unnecessary casts from
The function strtoul returns unsigned long and can be directly
assigned to a smaller type. Removing the casts allows easier
expansion of PCI domain.
Signed-off-by: Stephen Hemminger
---
lib/librte_eal/linuxapp/eal/eal_pci.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --gi
In some environments, the PCI domain can be larger than 16 bits.
For example, a PCI device passed through in Azure gets a synthetic domain
id which is internally generated based on GUID. The PCI standard does
not restrict domain to be 16 bits.
This change breaks ABI for API's that expose PCI addr
The PCI domain in Azure maybe 32 bits. When device is passed through
the domain is synthesize from the internal GUID.
Signed-off-by: Stephen Hemminger
---
drivers/net/mlx5/mlx5_ethdev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/n
> > The rte_ipv4_fragment_packet API expects that the link/interface MTU value
> > passed in be divisible by 8 bytes. Given the name of the parameter is
> > "mtu" rather than "frag_size" it is not necessarily the case that it will
> > be divisible by 8. An MTU of 1500 happens to produce a max fra
22/06/2017 17:56, Stephen Hemminger:
> In some environments, the PCI domain can be larger than 16 bits.
> For example, a PCI device passed through in Azure gets a synthetic domain
> id which is internally generated based on GUID. The PCI standard does
> not restrict domain to be 16 bits.
>
> This
22/06/2017 17:56, Stephen Hemminger:
> The PCI domain in Azure maybe 32 bits. When device is passed through
> the domain is synthesize from the internal GUID.
>
> Signed-off-by: Stephen Hemminger
> ---
> drivers/net/mlx5/mlx5_ethdev.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Do y
On Thu, 22 Jun 2017 18:05:42 +0200
Thomas Monjalon wrote:
> 22/06/2017 17:56, Stephen Hemminger:
> > In some environments, the PCI domain can be larger than 16 bits.
> > For example, a PCI device passed through in Azure gets a synthetic domain
> > id which is internally generated based on GUID.
On Thu, 22 Jun 2017 18:17:38 +0200
Thomas Monjalon wrote:
> 22/06/2017 17:56, Stephen Hemminger:
> > The PCI domain in Azure maybe 32 bits. When device is passed through
> > the domain is synthesize from the internal GUID.
> >
> > Signed-off-by: Stephen Hemminger
> > ---
> > drivers/net/mlx5/m
On Thu, 22 Jun 2017 18:17:38 +0200
Thomas Monjalon wrote:
> 22/06/2017 17:56, Stephen Hemminger:
> > The PCI domain in Azure maybe 32 bits. When device is passed through
> > the domain is synthesize from the internal GUID.
> >
> > Signed-off-by: Stephen Hemminger
> > ---
> > drivers/net/mlx5/m
22/06/2017 18:42, Stephen Hemminger:
> On Thu, 22 Jun 2017 18:17:38 +0200
> Thomas Monjalon wrote:
>
> > 22/06/2017 17:56, Stephen Hemminger:
> > > The PCI domain in Azure maybe 32 bits. When device is passed through
> > > the domain is synthesize from the internal GUID.
> > >
> > > Signed-off-b
On Wed, Jun 07, 2017 at 11:47:42AM +0100, Bruce Richardson wrote:
> Hi all,
>
> following on from the pressing need to add support in DPDK for detecting
> and managing external dependencies, I undertook to see what options we had.
> However, unrelated to this, over time, I have become increasingly
Document NIC features, add more information about them and add more
implementation related support.
Signed-off-by: Ferruh Yigit
---
Cc: Olivier Matz
v2:
* Add more details, mbuf and API fields
* Formatting added
TODO:
- Not all features all fully documented, need help from community
- Instead
Prior to new crypto patches for this release,
there were some fixes and some cleanup to do in
some crypto drivers, tests, sample apps and documents.
Changes in v2:
- Fixed too long lines
- Removed unnecessary AAD setting for 3DES/SHA1 test
Pablo de Lara (9):
crypto/aesni_mb: remove assert chec
For AES/DES tests, there is no need to leave out
the first block from the crypto operation.
Signed-off-by: Pablo de Lara
Acked-by: Fiona Trahe
---
test/test/test_cryptodev_perf.c | 14 ++
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/test/test/test_cryptodev_perf.c b
Some assert checks in the driver were
incorrect, but they are not necessary anyway,
as application will panic in any case.
Fixes: 0f548b50a160 ("crypto/aesni_mb: process crypto op on dequeue")
CC: sta...@dpdk.org
Signed-off-by: Pablo de Lara
---
drivers/crypto/aesni_mb/rte_aesni_mb_pmd.c | 4 --
AAD should not point at IV for AES algorithms.
For AES-GCM, AAD will point at additional data in the mbuf.
For the other algorithms (such as 3DES CBC), AAD is not used.
Fixes: ffbe3be0d4b5 ("app/test: add libcrypto")
CC: sta...@dpdk.org
Signed-off-by: Pablo de Lara
---
test/test/test_cryptodev_
Instead of using duplicated functions to get the algorithm
strings, use the functions from the cryptodev library.
Signed-off-by: Pablo de Lara
Acked-by: Fiona Trahe
---
test/test/test_cryptodev_perf.c | 119
1 file changed, 36 insertions(+), 83 deletions
Instead of passing the authentication and cipher offset
from the test vectors, just get them from the IV and AAD lengths.
Signed-off-by: Pablo de Lara
Acked-by: Fiona Trahe
---
test/test/test_cryptodev.c | 59 ++---
.../test/test_cryptodev_kasumi_hash_tes
Fixes: 4790f99d2d31 ("examples/l2fwd-crypto: use cryptodev algorithm parser")
CC: sta...@dpdk.org
Signed-off-by: Pablo de Lara
Acked-by: Fiona Trahe
---
examples/l2fwd-crypto/main.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/examples/l2fwd-crypto/main.c b/examples/l2fwd
Chain parameter can be CIPHER_HASH, HASH_CIPHER,
CIPHER_ONLY or HASH_ONLY, but only the first two
were shown in the application help.
Fixes: 1a75e9f3fadb ("examples/l2fwd-crypto: add cipher/hash only cases")
CC: sta...@dpdk.org
Signed-off-by: Pablo de Lara
Acked-by: Fiona Trahe
---
examples/l2
Fixes: ba7b86b1419b ("doc: add l2fwd-crypto sample app guide")
CC: sta...@dpdk.org
Signed-off-by: Pablo de Lara
Acked-by: Fiona Trahe
---
doc/guides/sample_app_ug/l2_forward_crypto.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/doc/guides/sample_app_ug/l2_forward_crypto
Fixes: f6cefe253cc8 ("app/crypto-perf: add range/list of sizes")
CC: sta...@dpdk.org
Signed-off-by: Pablo de Lara
Acked-by: Fiona Trahe
---
app/test-crypto-perf/cperf_options_parsing.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/app/test-crypto-perf/cperf_options_parsing
On Thu, Jun 22, 2017 at 01:14:54PM -0400, Neil Horman wrote:
> On Wed, Jun 07, 2017 at 11:47:42AM +0100, Bruce Richardson wrote:
> > Hi all,
> >
> > following on from the pressing need to add support in DPDK for detecting
> > and managing external dependencies, I undertook to see what options we h
Hello there,
Per our discussion within Intel, I am sending official request to DPDK
community to include our cloud network function framework YANFF -
https://www.github.com/intel-go/yanff to DPDK.org. As it is using DPDK
underneath and provides higher level abstraction for enabling development
On Thu, 22 Jun 2017 21:58:14 +
"Melik-Adamyan, Areg" wrote:
> Hello there,
>
> Per our discussion within Intel, I am sending official request to DPDK
> community to include our cloud network function framework YANFF -
> https://www.github.com/intel-go/yanff to DPDK.org. As it is using DPDK
> -Original Message-
> From: Stephen Hemminger [mailto:step...@networkplumber.org]
> Sent: Thursday, June 22, 2017 11:52 PM
> To: Chang, Cunyin
> Cc: dev@dpdk.org; Stephen Hemminger
> Subject: Re: [dpdk-dev] [PATCH 2/3] eal: PCI domain should be 32 bits
>
> On Thu, 22 Jun 2017 09:28:31
Tested-by: Peng, Yuan
- Tested Branch: dpdk-next-crypto/master
- Tested commit 18872f511c17a0a3591d4bfa5d56eefa5b85339c+7patches+this patch
- OS: 4.5.5-300.fc24.x86_64
- GCC: gcc version 6.1.1 20160510 (Red Hat 6.1.1-2) (GCC)
- CPU: Intel(R) Xeon(R) CPU E5-2699 v4 @ 2.20GHz
- NIC: Intel Corporati
Hi Gaetan,
Do you (or anyone else) have plan to move vdev bus into drivers/bus/.
Thanks,
Jianfeng
On 6/21/2017 7:36 AM, Gaetan Rivet wrote:
This patchset moves the PCI bus out of the EAL to the drivers/bus
subdirectory.
Almost all dependencies have been worked out, only remains KNI to be made
Since "rte_eal_dev_init()" has been removed, the comment referred to
it should be modified simultaneously.
Signed-off-by: Yong Wang
---
drivers/net/virtio/virtio_user_ethdev.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/virtio/virtio_user_ethdev.c
b/drivers/n
Hi Martin,
On Thursday, June 06/22/17, 2017 at 15:37:27 +0530, Martin Weiser wrote:
>These adapters support 100G link speed but the speed_capa bitmask in the
>device info did not reflect that.
>
>Signed-off-by: Martin Weiser
>---
> drivers/net/cxgbe/cxgbe_ethdev.c | 3 +++
>
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