On 03/10, Haiyue Wang wrote:
>The DCF (Device Config Function) needs the hardware index of the VFs to
>control the flow setting. And also if the VF resets, the index may be
>changed, so it should handle this in VF reset event.
>
>Signed-off-by: Haiyue Wang
>---
> drivers/net/ice/ice_dcf.c|
Hi Anoob,
Thank you.
Please see my answers below.
Regards,
Praveen
-Original Message-
From: Anoob Joseph
Sent: Thursday, March 12, 2020 4:31 PM
To: Shetty, Praveen ; dev@dpdk.org; Doherty, Declan
; Iremonger, Bernard ;
Ananyev, Konstantin
Subject: RE: [dpdk-dev] [PATCH v1] examples/
Hi Nicolas,
It is in my backlog to review this patchset.
Regards,
Akhil
> -Original Message-
> From: Chautru, Nicolas
> Sent: Friday, March 13, 2020 1:40 AM
> To: tho...@monjalon.net; Akhil Goyal ; dev@dpdk.org
> Cc: Yigit, Ferruh
> Subject: RE: [PATCH v3 00/14] bbdev new features
>
>
> Fixes: 3dd4435cf473 ("cryptodev: fix checks related to device id")
> Cc: sta...@dpdk.org
>
> Signed-off-by: Adam Dybkowski
> ---
Acked-by: Akhil Goyal
Hi Bruce,
> -Original Message-
> From: Bruce Richardson
> Sent: Wednesday, March 11, 2020 8:08 PM
> To: Morten Brørup
> Cc: Gavin Hu ; Ferruh Yigit ;
> dev@dpdk.org; nd ; david.march...@redhat.com;
> tho...@monjalon.net; ktray...@redhat.com; jer...@marvell.com;
> Honnappa Nagarahalli ; R
On 03/10, Haiyue Wang wrote:
>The DCF (Device Config Function) works at the user PF level, it can't
>access the real PF hardware directly. So it will proxy the PF's AdminQ
>command through DCF's mailbox.
>
>And the DCF is mainly used to control the flow setting of other VFs, so
>it only needs to in
On 03/13, Ye Xiaolong wrote:
>> struct ice_dcf_adapter {
>>+ struct ice_adapter parent; /* Must be first */
>>+
>> struct ice_dcf_hw real_hw;
>>- struct rte_ether_addr mac_addr;
>
>This one isn't needed at the first place.
My bad, please ignore this comment.
On Wed, Feb 26, 2020 at 5:53 PM Thomas Monjalon wrote:
>
> 26/02/2020 17:35, Jerin Jacob:
> > On Wed, Feb 26, 2020 at 8:31 PM Ferruh Yigit wrote:
> > >
> > > Signed-off-by: Ferruh Yigit
> >
> > Acked-by: Jerin Jacob
>
> Acked-by: Thomas Monjalon
Acked-by: David Marchand
btw, I did not find
For environments (such as containers) where hugetlbfs are not available,
some unit tests can be run with 'no-huge' option.
fast-tests suites is generated dynamically according to hugetlbfs
availability in building environment. This allows unit test to run
in different environments using the same s
Add Travis CI jobs to run unit tests on aarch64 platform.
Signed-off-by: Ruifeng Wang
Reviewed-by: Gavin Hu
---
.travis.yml | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/.travis.yml b/.travis.yml
index b64a81bd0..26d6bcb6d 100644
--- a/.travis.yml
+++ b/.travis.yml
@@
As fast-tests suite generated with only applicable cases included,
hugepage is not a mandatory to run the test.
Ignore the result of hugepage set up, so that validation in environment
without hugepage can proceed.
Signed-off-by: Ruifeng Wang
Reviewed-by: Gavin Hu
---
.ci/linux-setup.sh | 11 +++
When running with '--no-huge' flag, tests failed with messages as:
ACL context creation with invalid NUMA should have failed!
fbk hash creation should have failed
test_table_pipeline: Check pipeline invalid params failed.
These cases test against invalid socket ID as input parameter, a
In environments where hugepage are not available, such as
containers, many cases in fast-tests suite should also run
if no-huge EAL option is used.
Flag is appended to each case in fast-tests suite to indicate
whether it lives with no-huge mode.
With the flag, fast-tests suite can be generated bas
Hello, this is my report about my findings:
mlockall() takes a very short time for different transparent hugepage
configurations after using the fix in EAL. Log as follows:
** transparent_hugepage is madvise***
[root@X6000-C23-3U dpdk-19.11]# strace -T -e trace=mlockall ./build/app/test
On Wed, Feb 5, 2020 at 11:24 AM wrote:
>
> From: Jerin Jacob
>
> _cpuset TLS variable stores the CPU affinity of eal thread.
> Populate the _cpuset TLS variable for control thread to
>
> 1) Make rte_thread_get_affinity() and eal_thread_dump_affinity
> functional with control thread.
> 2) Quick ac
On Wed, Feb 26, 2020 at 8:50 PM David Christensen
wrote:
>
> Bare metal PowerNV systems include a DPDK supported IOMMU that allows
> IOVA=VA support. Test for the platform type and report virtual address
> support if running on a PowerNV system.
I can't test it, so I'll trust you on this :-).
Com
The user space DPDK rte_cio_rmb barrier in definition corresponds to the
kernel dma_rmb barrier on all supported architectures[1][2][3].
As it is called in the data path[4], redefine it to relax the barrier and
uplift the performance.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/
rte_cio_wmb is a light weight version of IO memory barrier that
guarantees that the stores to the coherent memory prior to the
the rte_cio_rmb() call are visible to the NIC HW before the doorbell
ring(or any other stores to the MMIO registers) that follows it.[1]
Fixes: 5e02e19eb14e ("net/ena: fix
To gaurantee the update observed by NIC HW, a cio barrier is sufficient,
a io barrier, which translates to dsb on aarch64, is overkill.
Suggested-by: Honnappa Nagarahalli
Signed-off-by: Gavin Hu
Reviewed-by: Honnappa Nagarahalli
---
drivers/net/ena/base/ena_eth_com.c | 2 +-
1 file changed, 1
To ensure the stores to the host memory are observed by NIC HW before a
door bell ring to the NIC HW and the HW starts actions, for example,
doing DMA, a barrier is required on weak memory ordering platforms, like
aarch64.
However, unnecessarily too strong barriers like 'dsb' on aarch64 will
dampe
To gaurantee the update observed by NIC HW, a cio barrier is sufficient,
an io barrier, which translates to dsb on aarch64, is overkill.
Suggested-by: Honnappa Nagarahalli
Signed-off-by: Gavin Hu
Reviewed-by: Honnappa Nagarahalli
---
drivers/net/ena/base/ena_eth_com.h | 4 +++-
1 file changed,
The statistics logging are in the data path, as rte_atomic APIs enforce
unnecessary barriers on aarch64, this patch uses c11 atomic APIs with
the __ATOMIC_RELAXED memory ordering to give CPU more freedom to optimize
by making use of out-of-order execution.
Signed-off-by: Gavin Hu
Reviewed-by: Hon
As there is necessary barriers before calling the function everywhere,
then using the relaxed write function ENA_REG_WRITE32_RELAXED is ok.
Fixes: 99ecfbf845b3 ("ena: import communication layer")
Cc: sta...@dpdk.org
Signed-off-by: Gavin Hu
Reviewed-by: Honnappa Nagarahalli
---
drivers/net/ena/
There is a memset operation for the whole structure so no need
to memset the sub fields in it.
Fixes: 1173fca25af9 ("ena: add polling-mode driver")
Cc: sta...@dpdk.org
Suggested-by: Honnappa Nagarahalli
Signed-off-by: Gavin Hu
Reviewed-by: Honnappa Nagarahalli
---
drivers/net/ena/ena_ethdev.c
Hi Bruce,
> -Original Message-
> From: Bruce Richardson
> Sent: Wednesday, March 11, 2020 8:08 PM
> To: Morten Brørup
> Cc: Gavin Hu ; Ferruh Yigit ;
> dev@dpdk.org; nd ; david.march...@redhat.com;
> tho...@monjalon.net; ktray...@redhat.com; jer...@marvell.com;
> Honnappa Nagarahalli ; R
Hello,
On Thu, Feb 27, 2020 at 6:34 PM Laatz, Kevin wrote:
>
> > The ep struct is used to track what type of stats are required by the
> > client.
> > For PORT_STATS type, it contains the lists of port and metric ids to query,
> > and
> > the number of ids in each list.
> >
> > The ep struct ha
On Sun, Mar 8, 2020 at 5:22 AM Haiyue Wang wrote:
> Use the 32bit typedef for structure 4B alignment marking.
>
> Fixes: 2b393160a480 ("eal: introduce structure markers")
> Cc: sta...@dpdk.org
>
> Signed-off-by: Haiyue Wang
Acked-by: Xiaolong Ye
Acked-by: Jerin Jacob
Applied, thanks.
--
Davi
On Mon, Mar 9, 2020 at 8:08 AM Jerin Jacob wrote:
>
> On Mon, Mar 9, 2020 at 11:47 AM Sunil Kumar Kori wrote:
> >
> > If user passes log-level eal parameter to enable log level based on regex
> > then in case of error message is being printed for pattern match instead of
> > regex. Following is t
On Mon, Mar 9, 2020 at 10:39 AM David Marchand
wrote:
>
> No need to export dsb and dmb.
> EAL memory barriers are the public API.
>
> %s/\<\(d.b\)\>(\([^()]*\))$/asm volatile("\1 \2" : : : "memory")/
>
> Signed-off-by: David Marchand
Reviewed-by: Gavin Hu
Acked-by: Jerin Jacob
Applied.
--
Two bugs in rx_queue_count function:
- One entry may contain several segments, so 'used' must be multiplied
by number of segments per entry to properly reflect the queue usage.
- rx_queue_count returns the number of entries used in queue, so it ranges
from 0 to max number of entries in queue, n
On Mon, Mar 9, 2020 at 3:55 PM David Marchand wrote:
>
> When the memory allocator reserves virtual addresses, it still does not
> know what they will be used for.
> Besides, huge areas are reserved for memory hotplug in multiprocess
> setups. But most of the pages are unused in the whole life of
On Wed, Mar 11, 2020 at 3:39 PM Harry van Haaren
wrote:
>
> This commit releases all service cores from their role,
> returning them to ROLE_RTE on rte_service_finalize().
>
> This may fix an issue relating to the service cores causing
s/may fix/fixes/
> a race-condition on eal_cleanup(), where
On Thu, Mar 12, 2020 at 2:09 AM Linhaifeng wrote:
>
> In order to get more accurate the cntvct_el0 reading,
> SW must invoke isb.
>
> Fixes: ccad39ea0712 ("eal/arm: add cpu cycle operations for ARMv8")
> Cc: sta...@dpdk.org
>
> Reviewed-by: Gavin Hu
Acked-by: Jerin Jacob
> Signed-off-by: Haifeng
This patch set introduced vectorized datapath for packed ring.
The size of packed ring descriptor is 16Bytes. Four batched descriptors
can just placed into one cacheline. AVX512 instructions can well handle
this kind of data. Packed ring TX datapath can fully transformed into
vectorized datapath.
Packed ring vectorized rx function won't support GUEST_TSO4 and
GUSET_TSO6. Adding "lro" parameter into virtio user vdev arguments
can disable these features for vectorized path selection.
Signed-off-by: Marvin Liu
diff --git a/drivers/net/virtio/virtio_user/virtio_user_dev.c
b/drivers/net/virt
Introduce free threshold setting in Rx queue. Now default value of Rx
free threshold is 32. Limiated threshold size to multiple of four as
only vectorized packed Rx function will utilize it. Virtio driver will
rearm Rx queue when more than threshold descs were dequeued.
Signed-off-by: Marvin Liu
Optimize packed ring Rx datapath when mergeable buffer and LRO are not
required. Solution of optimization is pretty like vhost, split batch
and single functions. Batch function will only dequeue those descs
whose cacheline are aligned. Also padding desc extra structure to 16
bytes aligned.
Signed-
Packed ring vectorized datapath can be selected when requirements are
fulfilled.
1. AVX512 is allowed by config file and compiler
2. VERSION_1 and in_order features are negotiated
3. ring size is power of two
4. LRO and mergeable feature disabled in Rx datapath
Signed-off-by: Marvin Liu
diff --
Move xmit offload and packed ring xmit enqueue function to header file.
These functions will be reused by packed ring vectorized Tx function.
Signed-off-by: Marvin Liu
diff --git a/drivers/net/virtio/virtio_rxtx.c b/drivers/net/virtio/virtio_rxtx.c
index ac417232b..b8b4d3c25 100644
--- a/drivers
Signed-off-by: Marvin Liu
diff --git a/drivers/net/virtio/meson.build b/drivers/net/virtio/meson.build
index 04c7fdf25..b0bddfd06 100644
--- a/drivers/net/virtio/meson.build
+++ b/drivers/net/virtio/meson.build
@@ -11,6 +11,7 @@ deps += ['kvargs', 'bus_pci']
if arch_subdir == 'x86'
sou
Optimize packed ring Tx datapath alike Rx datapath. Split Rx datapath
into batch and single Tx functions.
Signed-off-by: Marvin Liu
diff --git a/drivers/net/virtio/virtio_ethdev.h
b/drivers/net/virtio/virtio_ethdev.h
index 10e39670e..c9aaef0af 100644
--- a/drivers/net/virtio/virtio_ethdev.h
+++
Hi David,
> Hello,
>
> On Thu, Feb 27, 2020 at 6:34 PM Laatz, Kevin
> wrote:
> >
> > > The ep struct is used to track what type of stats are required by the
> client.
> > > For PORT_STATS type, it contains the lists of port and metric ids to
> > > query, and the number of ids in each list.
>
Acked-by: Dave Burley
On 04/03/2020 18:54, Nicolas Chautru wrote:
From: Nic Chautru
Adding capability flag for device variants when HARQ buffer
may or may not include the filler bits.
Minor cosmetic changes in same file.
Signed-off-by: Nic Chautru
---
lib/librte_bbdev/rte_bbdev.h| 2
Acked-by: Dave Burley
On 04/03/2020 18:54, Nicolas Chautru wrote:
From: Nic Chautru
This exposes the HARQ buffer size at the device driver level
instead of using the capability of a specific operation.
This is currently not yet used by a device until
future commit.
Signed-off-by: Nic Chautr
Hi Praveen,
Please see inline.
Thanks,
Anoob
> -Original Message-
> From: Shetty, Praveen
> Sent: Friday, March 13, 2020 12:36 PM
> To: Anoob Joseph ; Doherty, Declan
> ; Ananyev, Konstantin
> ; Iremonger, Bernard
> ; dev@dpdk.org
> Subject: [EXT] RE: [dpdk-dev] [PATCH v1] examples/ipse
Acked-by: Dave Burley
On 04/03/2020 18:54, Nicolas Chautru wrote:
From: Nic Chautru
Self-contained and cosmetic renaming of macro
so that to be more explicit for future extension.
Signed-off-by: Nic Chautru
---
app/test-bbdev/test_bbdev_perf.c | 51 +++-
Acked-by: Dave Burley
On 04/03/2020 18:54, Nicolas Chautru wrote:
From: Nic Chautru
Includes support for BLER wireless performance test with
new arguments for SNR and number of iterations for 5G.
Signed-off-by: Nic Chautru
---
app/test-bbdev/main.c| 29 ++-
app/test-bbdev/ma
Acked-by: Dave Burley
On 04/03/2020 18:54, Nicolas Chautru wrote:
From: Nic Chautru
Adding missing implementation for the interrupt tests
for LDPC encoder and decoders.
Signed-off-by: Nic Chautru
---
app/test-bbdev/test_bbdev_perf.c | 202 ++-
1 file c
Acked-by: Dave Burley
On 04/03/2020 18:54, Nicolas Chautru wrote:
From: Nic Chautru
Update related to the changes introduced by the
previous commits.
Signed-off-by: Nic Chautru
---
doc/guides/tools/testbbdev.rst | 337 +++--
1 file changed, 291 inserti
Acked-by: Dave Burley
On 04/03/2020 18:55, Nicolas Chautru wrote:
From: Nic Chautru
Supports for FEC 5G PMD Driver on FPGA card PAC N3000
Signed-off-by: Nic Chautru
---
config/common_base |5 +
doc/guides/bbdevs/fpga_5gnr_fec.rst| 297
Acked-by: Dave Burley
On 04/03/2020 18:55, Nicolas Chautru wrote:
From: Nic Chautru
Adding capacity to initialize the device driver from
the test-bbdev environment for the new device
FPGA for 5GNR FEC.
Signed-off-by: Nic Chautru
---
app/test-bbdev/Makefile | 3 +++
app/test-bbd
Acked-by: Dave Burley
On 04/03/2020 18:55, Nicolas Chautru wrote:
From: Nic Chautru
Adding missing overview page in documentation with
comparison of feature set by PMD implementation.
Signed-off-by: Nic Chautru
---
.gitignore | 1 +
doc/guides/bbdevs/fe
Nithin
On 3/12/20 12:18 PM, Nithin Dabilpuram wrote:
> Add support to traffic management api in OCTEON TX2 PMD.
> This support applies to CN96xx of C0 silicon version.
>
> This series depends on http://patchwork.dpdk.org/patch/66344/
>
> Depends-on:series-66344
If I understood the proposal corr
This patch adds 3DES CBC mode cipher algorithm.
Signed-off-by: Nagadheeraj Rottela
---
app/test/test_cryptodev.c | 1 +
app/test/test_cryptodev_des_test_vectors.h | 6 --
doc/guides/cryptodevs/features/nitrox.ini | 1 +
doc/guides/cryptodevs/nitrox.rst
Hi Anoob,
Please see my response inline.
Regards,
Praveen
-Original Message-
From: Anoob Joseph
Sent: Friday, March 13, 2020 4:22 PM
To: Shetty, Praveen ; Doherty, Declan
; Ananyev, Konstantin ;
Iremonger, Bernard ; dev@dpdk.org
Subject: RE: [dpdk-dev] [PATCH v1] examples/ipsec-secgw
Hi Adam,
> -Original Message-
> From: Dybkowski, AdamX
> Sent: Thursday, March 12, 2020 2:14 PM
> To: dev@dpdk.org; Trahe, Fiona ; akhil.go...@nxp.com
> Cc: Dybkowski, AdamX
> Subject: [PATCH 1/2] common/qat: get version of QAT firmware
>
> This patch adds the function for retrieving QA
Ruifeng Wang writes:
> For environments (such as containers) where hugetlbfs are not available,
> some unit tests can be run with 'no-huge' option.
>
> fast-tests suites is generated dynamically according to hugetlbfs
> availability in building environment. This allows unit test to run
> in diffe
Hi Adam,
> -Original Message-
> From: Dybkowski, AdamX
> Sent: Thursday, March 12, 2020 2:14 PM
> To: dev@dpdk.org; Trahe, Fiona ; akhil.go...@nxp.com
> Cc: Dybkowski, AdamX
> Subject: [PATCH 2/2] crypto/qat: handle mixed hash-cipher crypto on GEN2 QAT
>
> This patch adds handling of mi
Aaron Conole writes:
> Ruifeng Wang writes:
>
>> For environments (such as containers) where hugetlbfs are not available,
>> some unit tests can be run with 'no-huge' option.
>>
>> fast-tests suites is generated dynamically according to hugetlbfs
>> availability in building environment. This all
On Thu, Feb 27, 2020 at 6:34 PM Laatz, Kevin wrote:
>
> > The ep struct is used to track what type of stats are required by the
> > client.
> > For PORT_STATS type, it contains the lists of port and metric ids to query,
> > and
> > the number of ids in each list.
> >
> > The ep struct has values
On 03/10, Haiyue Wang wrote:
>The DCF (Device Config Function) works at the user PF level, it can't
>access the real PF hardware directly. So it will proxy the PF's AdminQ
>command through DCF's mailbox.
Proxy is a noun, so this sentence is a little bit confusing.
Do you mean DCF will rely on the
> -Original Message-
> From: Ye, Xiaolong
> Sent: Friday, March 13, 2020 22:07
> To: Wang, Haiyue
> Cc: dev@dpdk.org; Zhang, Qi Z ; Yang, Qiming
> ; Xing,
> Beilei ; Zhao1, Wei
> Subject: Re: [PATCH v2 6/7] net/ice: handle the PF initialization by DCF
>
> On 03/10, Haiyue Wang wrote:
>
This is a helper function in case components would like to do more work
than just logging a message based on log level, like for example
collecting some stats if the log type is DEBUG etc..
A few existing relevant usage converted to this new API.
Signed-off-by: Ferruh Yigit
Acked-by: Hyong Youb
This patch set adds handling of mixed hash-cipher algorithms
available on GEN2 QAT in particular firmware versions.
Also the documentation is updated to show the mixed crypto
algorithms are supported on QAT GEN2.
v2:
* minor fixes and improvements
Adam Dybkowski (2):
common/qat: get version of
This patch adds the function for retrieving QAT firmware
version, required to check the internal capabilities that
depend on the FW version.
Signed-off-by: Adam Dybkowski
---
drivers/common/qat/qat_adf/icp_qat_fw.h | 2 +
drivers/common/qat/qat_qp.c | 92 +
d
This patch adds handling of mixed hash-cipher algorithms
available on GEN2 QAT in particular firmware versions.
Also the documentation is updated to show the mixed crypto
algorithms are supported on QAT GEN2.
Signed-off-by: Adam Dybkowski
---
doc/guides/cryptodevs/qat.rst | 9 -
On Fri, Mar 13, 2020 at 12:08:05PM +0100, Andrzej Ostruszka wrote:
> External Email
>
> --
> Nithin
>
> On 3/12/20 12:18 PM, Nithin Dabilpuram wrote:
> > Add support to traffic management api in OCTEON TX2 PMD.
> > This support a
On Fri, Mar 13, 2020 at 2:04 PM Aaron Conole wrote:
>
> Aaron Conole writes:
>
> > Ruifeng Wang writes:
> >
> >> For environments (such as containers) where hugetlbfs are not available,
> >> some unit tests can be run with 'no-huge' option.
> >>
> >> fast-tests suites is generated dynamically ac
Acked-by: Dave Burley
On 04/03/2020 18:54, Nicolas Chautru wrote:
From: Nic Chautru
This is to support cases when the input data for
decoding a code block is larger than 64kB and would
not fit as a contiguous block of data into one
mbuf. In that case the length from the opearation
supersedes
This patch set is confusing to me. Only the DCF can deal with switch rules so
why is the ice PMD trying to do anything with switch rules related to DCF?
Paul
> -Original Message-
> From: dev On Behalf Of wei.zh...@intel.com
> Sent: Thursday, March 12, 2020 6:04 PM
> To: dev@dpdk.org
> C
> -Original Message-
> From: dev On Behalf Of wei.zh...@intel.com
> Sent: Thursday, March 12, 2020 6:04 PM
> To: dev@dpdk.org
> Cc: Zhang, Qi Z ; Ye, Xiaolong
> ; sta...@dpdk.org; Zhao1, Wei
>
> Subject: [dpdk-dev] [PATCH 5/7] net/ice: change default tunnle type
>
> The default tunnle
I'm confused. Shouldn't the DCF be a separate driver since it is a VF, not part
of a PF? You are starting to combine PF/VF code and I'm not sure if that is the
correct way to go.
Paul
> -Original Message-
> From: dev On Behalf Of Haiyue Wang
> Sent: Monday, March 9, 2020 11:50 PM
> To:
On 3/6/2020 9:57 AM, Hemant Agrawal wrote:
> Add the error handling on failure.
>
> Signed-off-by: Nipun Gupta
> Signed-off-by: Hemant Agrawal
[Copy/paste from v1 comment which put there by mistake]
Hi,
This commit seems doing,
- Fix 'dpaa2_put_qbman_swp()' which previously may reference the
Hi Paul,
Yes, it's VF (VF hardware initialization like virtchnl). But the flow setting
is the
ice PF AdminQ message, so the DCF shares most of ice PMD flow control.
BR,
Haiyue
> -Original Message-
> From: Stillwell Jr, Paul M
> Sent: Saturday, March 14, 2020 00:19
> To: Wang, Haiyue ;
Hi Haiyue,
This statement is confusing to me "But the flow setting is the ice PF AdminQ
message, so the DCF shares most of ice PMD flow control." What do you mean by
"flow setting"? The way I understand DCF working is that there is a trusted VF
(the DCF) that is setting switch rules for other V
Hi Paul,
> -Original Message-
> From: Stillwell Jr, Paul M
> Sent: Saturday, March 14, 2020 00:50
> To: Wang, Haiyue ; dev@dpdk.org; Ye, Xiaolong
> ; Zhang,
> Qi Z ; Yang, Qiming ; Xing,
> Beilei
> Cc: Zhao1, Wei
> Subject: RE: [dpdk-dev] [PATCH v2 0/7] add Intel DCF PMD support
>
>
OK, I looked at the code further and it seems like what you are doing is you
are using the iavf PCI device ID instead of the PF device ID when the user says
cap=dcf. This doesn't seem like the right thing to do. Why not modify the iavf
code to support being the DCF? Or create a new PMD? You are
>
> On Fri, Mar 6, 2020 at 8:25 PM Coyle, David wrote:
> >
> > > >
> > > > /** Error Detection Algorithms */
> > > > enum rte_rawdev_multi_fn_err_detect_algorithm {
> > > > RTE_RAWDEV_MULTI_FN_ERR_DETECT_CRC32_ETH,
> > >
> > > IMO, It does not make sense to add protocol specific stuff in
On Fri, Mar 13, 2020 at 11:30 PM Coyle, David wrote:
>
> >
> > On Fri, Mar 6, 2020 at 8:25 PM Coyle, David wrote:
> > >
> > > > >
> > > > > /** Error Detection Algorithms */
> > > > > enum rte_rawdev_multi_fn_err_detect_algorithm {
> > > > > RTE_RAWDEV_MULTI_FN_ERR_DETECT_CRC32_ETH,
> > >
This patch adds J0 capability to Intel QuickAssist Technology driver
Signed-off-by: Arek Kusztal
---
drivers/crypto/qat/qat_sym_capabilities.h | 8
drivers/crypto/qat/qat_sym_session.c | 11 ---
drivers/crypto/qat/qat_sym_session.h | 5 +
3 files changed, 17 inse
This patch adds crypto J0 test case to AES-GCM
Signed-off-by: Arek Kusztal
---
app/test/test_cryptodev.c | 28 ++--
app/test/test_cryptodev.h | 1 +
app/test/test_cryptodev_aead_test_vectors.h | 51 +
3 files changed, 7
On 13/03/2020 04:40, Li, Xiaoyun wrote:
> Hi
>
> This issue is already fixed in 20.02 with base code update of the following
> commit.
>
>
>
> commit 37b091c75b13d2f26359be9b77adbc33c55a7581
>
> Author: Xiaolong Ye
>
> Date: Mon Jan 13 10:39:31 2020 +0800
>
>
>
> net/i40e/base: ext
The versions currently listed as maintained have gone stale.
Rather than having to keep updating this doc, point to the
dpdk.org stable roadmap.
Signed-off-by: Kevin Traynor
---
doc/guides/contributing/stable.rst | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/doc/guides/c
> I suggest this change (I can send a patch fixing the issue in other .h files):
>
> +/*
> + * RTE_TOOLCHAIN_GCC is true if the target is built with GCC,
> + * while a host application (like pmdinfogen) may have another compiler.
> + * RTE_CC_IS_GNU is true if the file is compiled with GCC,
> + * n
> -Original Message-
> From: Stillwell Jr, Paul M
> Sent: Saturday, March 14, 2020 01:48
> To: Wang, Haiyue ; dev@dpdk.org; Ye, Xiaolong
> ; Zhang,
> Qi Z ; Yang, Qiming ; Xing,
> Beilei
> Cc: Zhao1, Wei ; Yigit, Ferruh
> Subject: RE: [dpdk-dev] [PATCH v2 0/7] add Intel DCF PMD support
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