On Fri, Mar 20, 2020 at 3:02 PM Kevin Traynor wrote:
>
> On 20/03/2020 09:53, Muhammad Bilal wrote:
> > On Fri, Mar 20, 2020 at 2:39 PM Luca Boccassi wrote:
> >>
> >> On Fri, 2020-03-20 at 13:02 +0500, Muhammad Bilal wrote:
> >>> in doc-clean removing the folder which contain
> >>> the text files
> From: dev [mailto:dev-boun...@dpdk.org] On Behalf Of Mattias Rönnblom
> Sent: Monday, March 23, 2020 6:35 PM
>
> On 2020-03-23 18:14, Honnappa Nagarahalli wrote:
> >
> >
> > Subject: Re: [dpdk-dev] Arm roadmap for 20.05
> >
> > On 2020-03-10 17:42, Honnappa Nagarahalli wrote:
>
implement set hash global configurations, set symmetric hash enable
and set hash input set in rte flow API.
Signed-off-by: Chenxu Di
---
v5:
-Modified the doc i40e.rst and various name.
v4:
-added check for l3 pctype with l4 input set.
v3:
-modified the doc i40e.rst
v2:
-canceled remove legacy f
On 3/20/20 2:15 PM, Zhang, Qi Z wrote:
>
>
>> -Original Message-
>> From: Thomas Monjalon
>> Sent: Friday, March 20, 2020 6:45 PM
>> To: Zhang, Qi Z
>> Cc: dev@dpdk.org; rahul.lakkire...@chelsio.com; Wang, Xiao W
>> ; xavier.hu...@huawei.com; Xing, Beilei
>> ; Lu, Wenzhuo ; Yang, Qiming
> -Original Message-
> From: Wang, ShougangX
> Sent: Friday, March 6, 2020 10:24 AM
> To: dev@dpdk.org
> Cc: Rong, Leyi ; Wu, Jingjing ;
> Wang,
> ShougangX
> Subject: [PATCH] net/iavf: unify Rx ptype table
>
> From: Wang Shougang
Acked-by: Jingjing Wu
Hi,
> -Original Message-
> From: dev On Behalf Of Raslan Darawsheh
> Sent: Monday, March 23, 2020 4:22 PM
> To: Matan Azrad ; Slava Ovsiienko
>
> Cc: dev@dpdk.org; sta...@dpdk.org
> Subject: [dpdk-dev] [PATCH] net/mlx5: fix validation of VXLAN/VXLAN-GPE
> specs
>
> Trying to create zero
On 3/9/20 11:27 AM, Olivier Matz wrote:
> Hi,
>
> On Mon, Mar 09, 2020 at 11:01:25AM +0800, Tonghao Zhang wrote:
>> On Sat, Mar 7, 2020 at 8:54 PM Andrew Rybchenko
>> wrote:
>>>
>>> On 3/7/20 3:51 PM, Andrew Rybchenko wrote:
On 3/6/20 4:37 PM, Jerin Jacob wrote:
> On Fri, Mar 6, 2020 at
Hi Ray,
I have tried to avoid hand unrolling loops and found the following observations.
1. Although it decreases LOC it also takes away readability too.
Example:
Avoiding unrolled code below
priv[0].u64[0] = rte_node_mbuf_priv1(mbuf[0])->u;
priv
Hi Chenxu,
> -Original Message-
> From: Di, ChenxuX
> Sent: Monday, March 23, 2020 9:19 AM
> To: Iremonger, Bernard ; dev@dpdk.org;
> Xing, Beilei ; Zhang, Qi Z ;
> Doherty, Declan
> Cc: Ananyev, Konstantin ; Iremonger,
> Bernard
> Subject: RE: [dpdk-dev] [PATCH 3/3] net/i40e: configure
On 3/20/20 2:29 PM, cha...@amd.com wrote:
> From: Chandu Babu N
>
> add support for RSS ethdev_ops reta_update, reta_query
> rss_hash_update, rss_hash_conf_get
The patch should update doc/guides/nics/features/axgbe.ini to
advertise corresponding features.
>
> Signed-off-by: Chandu Babu N
> --
Hi Dekel,
> -Original Message-
> Subject: [dpdk-dev] [PATCH] app/testpmd: enhance GTP support
>
> This patch adds CLI option to enter the v_pt_rsv_flags value for GTP
> flow pattern item.
> It also adds GTP as valid item in raw_encap nad raw_decap setting.
>
> Signed-off-by: Dekel Peled
On Mon, Mar 23, 2020 at 8:59 PM David Marchand
wrote:
>
> This is a respin of Ruifeng series with a patch I sent earlier today.
>
> Changelog since v3:
> - patch 1 is new,
> - patch 3 is the only that has differences,
Series applied, thanks Ruifeng.
Small note, in containers all cores from the t
[AMD Official Use Only - Internal Distribution Only]
RSS functionality is already supported by AXGBE and it is updated in
doc/guides/nics/features/axgbe.ini accordingly.
This patch adds support to update RSS Hash key and RETA.
Regards,
Chandu
-Original Message-
From: Andrew Rybchenko
On 3/16/20 3:52 PM, BillZhou wrote:
> One of the reasons to destroy a flow is the fact that no packet matches the
> flow for "timeout" time.
> For example, when TCP\UDP sessions are suddenly closed.
>
> Currently, there is no any dpdk mechanism for flow aging and the
> applications use there own w
On 3/24/20 1:17 PM, Namburu, Chandu-babu wrote:
> [AMD Official Use Only - Internal Distribution Only]
>
> RSS functionality is already supported by AXGBE and it is updated in
> doc/guides/nics/features/axgbe.ini accordingly.
> This patch adds support to update RSS Hash key and RETA.
What about
Hi Konstantin,
> >
> > > Subject: RE: [PATCH v3 06/12] ipsec: optimize with c11 atomic for sa
> outbound
> > > sqn update
> > >
> > > Hi Phil,
> > >
> > > >
> > > > For SA outbound packets, rte_atomic64_add_return is used to
> generate
> > > > SQN atomically. This introduced an unnecessary full b
Hi Phil,
>
> > >
> > > > Subject: RE: [PATCH v3 06/12] ipsec: optimize with c11 atomic for sa
> > outbound
> > > > sqn update
> > > >
> > > > Hi Phil,
> > > >
> > > > >
> > > > > For SA outbound packets, rte_atomic64_add_return is used to
> > generate
> > > > > SQN atomically. This introduced a
This patch updates the MLX5 PMD documentations, adding Flex parser
settings and correcting minimal versions numbers.
Signed-off-by: Dekel Peled
---
doc/guides/nics/mlx5.rst | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/n
In the current state, when preforming read/write
transactions we must wait for a completion in order
to run the next transaction, and all transactions are
performed by order.
Relaxed Ordering is a PCI optimization which by enabling it
we allow the system to perform read/writes in a different
order
This patch set adds CPU flags which will enable the detection of ISA
features available on more recent x86 based CPUs.
The CPUID leaf information can be found in Section 1.7 of this
document:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-progr
Add the CPU flag for AVX-512 conflict detection instructions.
Signed-off-by: Kevin Laatz
---
lib/librte_eal/common/arch/x86/rte_cpuflags.c | 1 +
lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/lib/librte_eal/common/arch/x86/rte
Add the CPU flag for AVX-512 doubleword and quadword instructions.
Signed-off-by: Kevin Laatz
---
lib/librte_eal/common/arch/x86/rte_cpuflags.c | 2 ++
lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/lib/librte_eal/common/arch/
Add the CPU flag for AVX-512 integer fused multiply-add instructions.
Signed-off-by: Kevin Laatz
---
lib/librte_eal/common/arch/x86/rte_cpuflags.c | 1 +
lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/lib/librte_eal/common/arch
Add the CPU flag for AVX-512 vector bit manipulation 2 instructions.
Signed-off-by: Kevin Laatz
---
lib/librte_eal/common/arch/x86/rte_cpuflags.c | 1 +
lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/lib/librte_eal/common/arch/
Add the CPU flag for AVX-512 byte and word instructions.
Signed-off-by: Kevin Laatz
---
lib/librte_eal/common/arch/x86/rte_cpuflags.c | 1 +
lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/lib/librte_eal/common/arch/x86/rte_cpuf
Add the CPU flag for Galois field new instructions.
Signed-off-by: Kevin Laatz
---
lib/librte_eal/common/arch/x86/rte_cpuflags.c | 1 +
lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.
Add the CPU flag for AVX-512 vector length instructions.
Signed-off-by: Kevin Laatz
---
lib/librte_eal/common/arch/x86/rte_cpuflags.c | 1 +
lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/lib/librte_eal/common/arch/x86/rte_cpuf
Add the CPU flag for AVX-512 vector bit manipulation instructions.
Signed-off-by: Kevin Laatz
---
lib/librte_eal/common/arch/x86/rte_cpuflags.c | 1 +
lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/lib/librte_eal/common/arch/x8
Add the CPU flag for vector AES instructions.
Signed-off-by: Kevin Laatz
---
lib/librte_eal/common/arch/x86/rte_cpuflags.c | 1 +
lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
b/l
Add the CPU flag for AVX-512 vector neural network instructions.
Signed-off-by: Kevin Laatz
---
lib/librte_eal/common/arch/x86/rte_cpuflags.c | 1 +
lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/lib/librte_eal/common/arch/x86/
Add the CPU flag for vector carry-less multiply instructions.
Signed-off-by: Kevin Laatz
---
lib/librte_eal/common/arch/x86/rte_cpuflags.c | 1 +
lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/lib/librte_eal/common/arch/x86/rte
Add the CPU flag for AVX-512 vector popcount instructions.
Signed-off-by: Harry van Haaren
Signed-off-by: Kevin Laatz
---
lib/librte_eal/common/arch/x86/rte_cpuflags.c | 1 +
lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/lib/
Add the CPU flag for cache line demote instructions.
Signed-off-by: Kevin Laatz
---
lib/librte_eal/common/arch/x86/rte_cpuflags.c | 1 +
lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags
Add the CPU flag AVX-512 for bit algorithm instructions.
Signed-off-by: Kevin Laatz
---
lib/librte_eal/common/arch/x86/rte_cpuflags.c | 1 +
lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/lib/librte_eal/common/arch/x86/rte_cpuf
Add the CPU flag for direct store instructions.
Signed-off-by: Kevin Laatz
---
lib/librte_eal/common/arch/x86/rte_cpuflags.c | 1 +
lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
b
Add the CPU flag for direct store 64B instructions.
Signed-off-by: Kevin Laatz
---
lib/librte_eal/common/arch/x86/rte_cpuflags.c | 1 +
lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.
Add the CPU flag for AVX-512 two register intersection instructions.
Signed-off-by: Kevin Laatz
---
lib/librte_eal/common/arch/x86/rte_cpuflags.c | 1 +
lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/lib/librte_eal/common/arch/
If packets with the same metadata are received with compressed CQE
the metadata value is not copied from the title packet in vectorized
rx_burst routines, it causes wrong metadat values seeing by
applications.
Fixes: a18ac6113331 ("net/mlx5: add metadata support to Rx datapath")
Cc: sta...@dpdk.or
From: Pavan Nikhilesh
Current l2fwd-event application statically configures adjacent ports as
destination ports for forwarding the traffic.
Add a config option to pass the forwarding port pair mapping which allows
the user to configure forwarding port mapping.
If no config argument is specified
From: Pavan Nikhilesh
Current l2fwd-event application statically configures adjacent ports as
destination ports for forwarding the traffic.
Add a config option to pass the forwarding port pair mapping which allows
the user to configure forwarding port mapping.
If no config argument is specified
Hi, PSB.
> -Original Message-
> From: Ori Kam
> Sent: Tuesday, March 24, 2020 11:59 AM
> To: Dekel Peled ; wenzhuo...@intel.com;
> jingjing...@intel.com; bernard.iremon...@intel.com
> Cc: Matan Azrad ; dev@dpdk.org
> Subject: RE: [dpdk-dev] [PATCH] app/testpmd: enhance GTP support
>
> Hi
On Tue, Mar 24, 2020 at 5:36 PM Andrew Rybchenko
wrote:
>
> On 3/9/20 11:27 AM, Olivier Matz wrote:
> > Hi,
> >
> > On Mon, Mar 09, 2020 at 11:01:25AM +0800, Tonghao Zhang wrote:
> >> On Sat, Mar 7, 2020 at 8:54 PM Andrew Rybchenko
> >> wrote:
> >>>
> >>> On 3/7/20 3:51 PM, Andrew Rybchenko wrote
Hi Chenxu,
> -Original Message-
> From: dev On Behalf Of Chenxu Di
> Sent: Tuesday, March 24, 2020 8:18 AM
> To: dev@dpdk.org
> Cc: Yang, Qiming ; Xing, Beilei
> ; Zhao1, Wei ; Di, ChenxuX
>
> Subject: [dpdk-dev] [PATCH v5] net/i40e: implement hash function in rte
> flow API
>
> impleme
On 24/03/2020 07:04, Muhammad Bilal wrote:
> On Fri, Mar 20, 2020 at 3:02 PM Kevin Traynor wrote:
>>
>> On 20/03/2020 09:53, Muhammad Bilal wrote:
>>> On Fri, Mar 20, 2020 at 2:39 PM Luca Boccassi wrote:
On Fri, 2020-03-20 at 13:02 +0500, Muhammad Bilal wrote:
> in doc-clean removin
When creating a hairpin queue, the total data size and the maximal
number of packets are interrelated. The differ is the stride size.
Larger buffer size means big packet like jumbo could be supported,
but in the meanwhile, it will introduce more cache misses and have a
side effect on the performanc
Flow rule in NIC table on VF representor should not contain VLAN pop
or push actions, and encap or decap actions. Using these actions in
NIC table on VF representor is not a valid use case.
This patch updates the various validation functions to reject such
rules.
Cc: sta...@dpdk.org
Signed-off-by
> > > > > For SA outbound packets, rte_atomic64_add_return is used to
> > > > > generate SQN atomically. This introduced an unnecessary full
> > > > > barrier by calling the '__sync' builtin implemented rte_atomic_XX
> > > > > API on aarch64. This patch optimized it with c11 atomic and
> > > > >
> -Original Message-
> From: dev On Behalf Of Ananyev, Konstantin
> Sent: Tuesday, March 24, 2020 1:10 PM
> To: Honnappa Nagarahalli ; Phil Yang
> ; tho...@monjalon.net; Van Haaren,
> Harry ; step...@networkplumber.org;
> maxime.coque...@redhat.com; dev@dpdk.org; Richardson, Bruce
>
From: Matan Azrad
When both, direct and indirect notifier management cannot be
configured, return an error.
Signed-off-by: Matan Azrad
Acked-by: Viacheslav Ovsiienko
---
drivers/vdpa/mlx5/mlx5_vdpa_virtq.c | 30 --
1 file changed, 20 insertions(+), 10 deletions(-)
From: Matan Azrad
The configure and close operations may be called a lot of time by vhost
library according to the virtio connections in the guest.
VAR is the device memory space for the virtio queues doorbells.
Each VAR page can be shared for more than one queue while its owner must
synchronize
From: Matan Azrad
Add support for the next 2 callbacks:
get_vfio_device_fd and get_notify_area.
This will allow direct HW doorbell ringing from guest and will save CPU
usage in host.
By this patch, the QEMU will map the physical address of the virtio
device in guest directly to the physical add
In order to save CPU usage in host and even make it 0 when guest work with poll
mode,
add support for direct doorbell ringing.
Now, when the feature is supported in QEMU, the guest doorbell address is
mapped directly to the HW doorbell space and the host SW relay is not used.
Matan Azrad (4):
From: Matan Azrad
Add log prints to improve driver status following.
Signed-off-by: Matan Azrad
Acked-by: Viacheslav Ovsiienko
---
drivers/vdpa/mlx5/mlx5_vdpa.c | 2 ++
drivers/vdpa/mlx5/mlx5_vdpa_steer.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/vdpa/mlx5/mlx5_vdpa
On 24/03/2020 09:40, Pavan Nikhilesh Bhagavatula wrote:
> Hi Ray,
>
> I have tried to avoid hand unrolling loops and found the following
> observations.
>
> 1. Although it decreases LOC it also takes away readability too.
> Example:
> Avoiding unrolled code below
[SNIP]
>
Invalidation of consumed CQEs incurs a performance penalty
due to many cache misses caused by a non-sequential CQEs access.
Prefetch CQEs to get a better data locality and speed up the
decompression of CQEs. Prefetching reduces CPI rate of the
rxq_cq_decompress_v() function from 1 to 0.85 in my env
This patch set will remove the flow rules cache and move to the
non-cached mode for both DV and Verbs mode.
In the device closing stage, all the software resources for flows
created will be freed and corresponding hardware resources will be
released. Then the total cost of the memory will be reduc
When stopping a mlx5 device, all the flows inserted will be flushed
since they are with non-cached mode. And no more action will be done
for these flows in the device closing stage.
If the device restarts after stopped, no flow with non-cached mode
will be re-inserted.
The flush operation through r
Common structures used for mlx5 flow creating and destroying are
reorganized in order to separating the parts only for destroying
from all the items.
The "mlx5_flow" will contain the common items of DV and Verbs flow,
specific items for DV / Verbs only. These items will only be used
when creating a
Only the members of flow handle structure will be used when trying
to destroy a flow. Other members of mlx5 device flow resource will
only be used for flow creating, and they could be reused for different
flows.
So only the device flow handle structure needs to be saved for further
usage. This coul
By default, flows are categorized into two types of a mlx5 device.
1. The PMD driver will create some default flows to enable the
traffic and give some default behaviors on the packets. And
this is transparent to the upper layer application.
2. Other flows will be created in the appli
Hi,
We are currently having an issue when running the command to set up the DTS
with T-Rex on the machines.
We tried to look into the code, but we are still not sure why and what
cause the issue.
Do you have any clue how we can fix this? We know the DTS working, T-Rex
is able to be detected.
Be
This patch set will remove the flow rules cache and move to the
non-cached mode for both DV and Verbs mode.
In the device closing stage, all the software resources for flows
created will be freed and corresponding hardware resources will be
released. Then the total cost of the memory will be reduc
Common structures used for mlx5 flow creating and destroying are
reorganized in order to separating the parts only for destroying
from all the items.
The "mlx5_flow" will contain the common items of DV and Verbs flow,
specific items for DV / Verbs only. These items will only be used
when creating a
When stopping a mlx5 device, all the flows inserted will be flushed
since they are with non-cached mode. And no more action will be done
for these flows in the device closing stage.
If the device restarts after stopped, no flow with non-cached mode
will be re-inserted.
The flush operation through r
Only the members of flow handle structure will be used when trying
to destroy a flow. Other members of mlx5 device flow resource will
only be used for flow creating, and they could be reused for different
flows.
So only the device flow handle structure needs to be saved for further
usage. This coul
By default, flows are categorized into two types of a mlx5 device.
1. The PMD driver will create some default flows to enable the
traffic and give some default behaviors on the packets. And
this is transparent to the upper layer application.
2. Other flows will be created in the appli
The log file may be useful.
On Tue, Mar 24, 2020 at 11:32 AM David Liu wrote:
> Hi,
>
> We are currently having an issue when running the command to set up the
> DTS with T-Rex on the machines.
> We tried to look into the code, but we are still not sure why and what
> cause the issue.
>
> Do you
From: Alexander Kozyrev
> Invalidation of consumed CQEs incurs a performance penalty due to many
> cache misses caused by a non-sequential CQEs access.
> Prefetch CQEs to get a better data locality and speed up the decompression
> of CQEs. Prefetching reduces CPI rate of the
> rxq_cq_decompress_
From: Viacheslav Ovsiienko
> If packets with the same metadata are received with compressed CQE the
> metadata value is not copied from the title packet in vectorized rx_burst
> routines, it causes wrong metadat values seeing by applications.
>
> Fixes: a18ac6113331 ("net/mlx5: add metadata sup
From: Dekel Peled
> This patch updates the MLX5 PMD documentations, adding Flex parser
> settings and correcting minimal versions numbers.
>
> Signed-off-by: Dekel Peled
Acked-by: Matan Azrad
> ---
> doc/guides/nics/mlx5.rst | 14 +++---
> 1 file changed, 11 insertions(+), 3 deletio
From: Pavan Nikhilesh
Add device arguments to lock NPA aura and pool contexts in NDC cache.
The device args take hexadecimal bitmask where each bit represent the
corresponding aura/pool id.
Example:
-w 0002:02:00.0,npa_lock_mask=0xf // Lock first 4 aura/pool ctx
Signed-off-by: Pavan Nikh
From: Pavan Nikhilesh
Add device arguments to lock Rx/Tx contexts.
Application can either choose to lock Rx or Tx contexts by using
'lock_rx_ctx' or 'lock_tx_ctx' respectively per each port.
Example:
-w 0002:02:00.0,lock_rx_ctx=1 -w 0002:03:00.0,lock_tx_ctx=1
Signed-off-by: Pavan Nikhil
> > Subject: Re: [dpdk-dev] Arm roadmap for 20.05
> >
> > On 2020-03-10 17:42, Honnappa Nagarahalli wrote:
> >> Hello,
> >>Following are the work items planned for 20.05:
> >>
> >> 1) Use C11 atomic APIs in timer library
> >> 2) Use C11 atomic APIs in servi
https://bugs.dpdk.org/show_bug.cgi?id=421
Bug ID: 421
Summary: gcc 10.0.1 stringops-overflow warnings
Product: DPDK
Version: 20.05
Hardware: All
OS: Linux
Status: UNCONFIRMED
Severity: normal
Pri
Hi Vladimir,
> Change hash function from jhash to crc.
> Precalculate hash signatures for a bulk of keys and then
> use rte_hash_lookup_with_hash_bulk_data() to speed up sad lookup
Looks good in general.
Few thoughts below, nothing major.
> Signed-off-by: Vladimir Medvedkin
> ---
> This patch
(apologies Morten - I missed your response, consolidating the discussion in
this thread)
+ Intel x86 and IBM POWER maintainers
>
> > > Subject: Re: [dpdk-dev] Arm roadmap for 20.05
> > >
> > > On 2020-03-10 17:42, Honnappa Nagarahalli wrote:
> > >> Hello,
> > >> Follow
On 2020-03-23 23:19, Jerin Jacob wrote:
On Mon, Mar 23, 2020 at 11:11 PM dwilder wrote:
Thanks you for your review Jerin. See my responses are inline.
On 2020-03-20 06:24, Jerin Jacob wrote:
> On Fri, Feb 21, 2020 at 4:22 AM David Wilder
> wrote:
>>
>> If --no-huge is set and iova-mode has
Hi Akhil,
Checking again whether you have an estimate for this patchset review?
Thanks
Nic
-Original Message-
From: Akhil Goyal
Sent: Friday, March 13, 2020 12:15 AM
To: Chautru, Nicolas ; tho...@monjalon.net;
dev@dpdk.org
Cc: Yigit, Ferruh
Subject: RE: [PATCH v3 00/14] bbdev new feat
__ppc_get_timebase() reads and returns the current value of the Time
Base Register. It's more efficient as it uses the processor’s time
base facility directly
the DPDK on FreeBSD currently is not supported on Powerpc64, it should
be safe to include the sys/platform/ppc.h
Signed-off
It seems it caused by that dts not compatible with pexpect 4.8.0 , we met it
before, and we have fixed it in latest version.
Here are 3 options for you:
1, lower pexpect to 4.2.1
2, update dts to latest commit
3, apply the patch set below:
Add memory pre-allocation note for vhost example when enabling
"builtin-net-driver".
Signed-off-by: Xuan Ding
---
doc/guides/sample_app_ug/vhost.rst | 6 ++
1 file changed, 6 insertions(+)
diff --git a/doc/guides/sample_app_ug/vhost.rst
b/doc/guides/sample_app_ug/vhost.rst
index a71ada654.
This patch is intended to add iavf_dev_reset ops, enable iavf to support
"port reset all".
Signed-off-by: Lunyuan Cui
---
drivers/net/iavf/iavf_ethdev.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c
index
From: Yunjian Wang
The assert checks is not necessary, the gso_ctx is always non-NULL.
Fixes: 050316a88313 ("net/tap: support TSO (TCP Segment Offload)")
CC: sta...@dpdk.org
Signed-off-by: Yunjian Wang
---
drivers/net/tap/rte_eth_tap.c | 3 ---
drivers/net/tap/tap_intr.c| 1 -
2 files cha
Adding support for the following,
1. AES-192-GCM
2. AES-256-GCM
3. AES-192-CBC
Signed-off-by: Anoob Joseph
Signed-off-by: Tejasree Kondoj
---
examples/ipsec-secgw/ipsec.h | 2 +-
examples/ipsec-secgw/sa.c| 25 +
2 files changed, 26 insertions(+), 1 deletion(-)
diff
The main changes include:
* Update X722/X710 FW API version to 1.10.
* New device ID introduced for V710-T*L 5G.
* add constants for PTP pins.
Jiaqi Min (3):
net/i40e/base: update X722/X710 FW API version to 1.10
net/i40e/base: new device ID introduced for V710-TL 5G
net/i40e/base: add cons
This change is adding new device ID and handling it in the same
way as X710-T*L head of family. A new device ID is for new V710-T*L adapter
supporting speeds up to 5G.
Signed-off-by: Zalfresso-Jundzillo
Signed-off-by: Jiaqi Min
---
drivers/net/i40e/base/i40e_common.c | 12 +---
drivers/
update X722/X710 FW API version to 1.10.
Signed-off-by: Piotr Azarewicz
Signed-off-by: Jiaqi Min
---
drivers/net/i40e/base/i40e_adminq_cmd.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h
b/drivers/net/i40e/base/i40e_adminq_cmd.h
Introduce constants for handling PTP pins used for external
clock source.
Signed-off-by: Piotr Kwapulinski
Signed-off-by: Jiaqi Min
---
drivers/net/i40e/base/i40e_register.h | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/net/i40e/base/i40e_register.h
b/drivers/net/i40e/base/i4
[AMD Public Use]
Thank you Andrew, will update these in v2 patch.
-Original Message-
From: Andrew Rybchenko
Sent: Tuesday, March 24, 2020 3:55 PM
To: Namburu, Chandu-babu ; dev@dpdk.org
Cc: Kumar, Ravi1 ; Somalapuram, Amaranath
Subject: Re: [dpdk-dev] [PATCH v1] net/axgbe: add RSS re
Add memory pre-allocation note for vhost example when enabling
"builtin-net-driver".
Signed-off-by: Xuan Ding
---
v2:
* Modified expression in doc to make it more accurate.
---
doc/guides/sample_app_ug/vhost.rst | 7 +++
1 file changed, 7 insertions(+)
diff --git a/doc/guides/sample_app_ug
This patch set fixed a bug of vmdq example,
and added a documentation for it.
*** BLURB HERE ***
Junyu Jiang (2):
doc: add user guide for VMDq
examples/vmdq: fix RSS configuration
MAINTAINERS | 1 +
doc/guides/sample_app_ug/index.rst | 1 +
doc
currently, there is no documentation for vmdq example,
this path added the user guide for vmdq.
Signed-off-by: Junyu Jiang
---
MAINTAINERS | 1 +
doc/guides/sample_app_ug/index.rst | 1 +
doc/guides/sample_app_ug/vmdq_forwarding.rst | 208 ++
In order that all queues of pools can receive packets,
add enable-rss argument to change rss configuration.
Fixes: 6bb97df521aa ("examples/vmdq: new app")
Cc: sta...@dpdk.org
Signed-off-by: Junyu Jiang
Acked-by: Xiaoyun Li
---
doc/guides/sample_app_ug/vmdq_forwarding.rst | 6 +--
examples/vmd
On Tue, Mar 24, 2020 at 10:23 PM wrote:
>
> From: Pavan Nikhilesh
>
> Add device arguments to lock NPA aura and pool contexts in NDC cache.
> The device args take hexadecimal bitmask where each bit represent the
> corresponding aura/pool id.
> Example:
> -w 0002:02:00.0,npa_lock_mask=0xf
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