On Mon, 2017-07-03 at 22:51 +0200, Thomas Monjalon wrote:
> 12/05/2017 12:15, Ashwin Sekhar T K:
> >
> > Moved the definition of GCC_VERSION from lib/librte_table/rte_lru.h
> > to lib/librte_eal/common/include/rte_common.h.
> >
> > Tested compilation on:
> > * arm64 with gcc
> > * x86 with gcc
This license is already there in many files in examples/performance-
thread directory.
There are two cases in my patch.
1.
I moved some code from examples/performance-thread/common/lthread.c to
examples/performance-thread/common/arch/x86/stack.h.
lthread.c already has the below kind of license.
On Thu, 2017-05-18 at 14:25 +0530, Jerin Jacob wrote:
> -Original Message-
> >
> > Date: Thu, 18 May 2017 00:34:26 -0700
> > From: Ashwin Sekhar T K
> > To: jerin.ja...@caviumnetworks.com, john.mcnam...@intel.com,
> > jianbo@linaro.org
> > Cc: dev@dpdk.org, Ashwin Sekhar T K > om>
>
On Thu, 2017-05-18 at 14:35 +0800, Jianbo Liu wrote:
> On 18 May 2017 at 02:44, Jerin Jacob
> wrote:
> >
> > -Original Message-
> > >
> > > Date: Wed, 17 May 2017 11:19:49 -0700
> > > From: Ashwin Sekhar T K
> > > To: jerin.ja...@caviumnetworks.com, john.mcnam...@intel.com,
> > > jianb
On Mon, 2017-05-15 at 11:34 +0800, Jianbo Liu wrote:
> Use ARM NEON intrinsics to accelerate l3 fowarding.
>
> Signed-off-by: Jianbo Liu
Acked-by: Ashwin Sekhar T K
> ---
> examples/l3fwd/l3fwd_em.c| 4 +-
> examples/l3fwd/l3fwd_em_hlm.h| 17 ++-
> examples/l3fwd/l3fwd_em
On Fri, 2017-05-12 at 16:49 +0800, Jianbo Liu wrote:
> On 12 May 2017 at 15:25, Sekhar, Ashwin
> wrote:
> >
> > On Fri, 2017-05-12 at 13:51 +0800, Jianbo Liu wrote:
> > >
> > > On 9 May 2017 at 17:53, Ashwin Sekhar T K
> > > wrote:
> > >
On Fri, 2017-05-12 at 13:51 +0800, Jianbo Liu wrote:
> On 9 May 2017 at 17:53, Ashwin Sekhar T K
> wrote:
> >
> > Added CRC compute APIs for arm64 utilizing the pmull
> > capability
> >
> > Added new file net_crc_neon.h to hold the arm64 pmull
> > CRC implementation
> >
> > Verified the changes
The warning comes only when CFLAGS "-g -ggdb" are given and this seems
to be an issue with clang. I am seeing some related bugs on llvm
mailing list.
https://www.mail-archive.com/llvm-bugs@lists.llvm.org/msg05498.html
http://lists.llvm.org/pipermail/llvm-bugs/2016-July/048288.html
Even a simple c
On Thu, 2017-05-11 at 18:01 +0800, Jianbo Liu wrote:
> On 11 May 2017 at 17:49, Sekhar, Ashwin
> wrote:
> >
> > Hi Jianbo,
> >
> > Thanks for v3. Small compilation error. See inline comment.
> > Otherwise
> > it looks fine.
> >
> &g
Hi Jianbo,
Thanks for v3. Small compilation error. See inline comment. Otherwise
it looks fine.
On Thu, 2017-05-11 at 17:25 +0800, Jianbo Liu wrote:
> Use ARM NEON intrinsics to accelerate l3 fowarding.
>
> Signed-off-by: Jianbo Liu
> ---
[...]
> +/**
> + * Process one packet:
> + * Update sou
On Thu, 2017-05-11 at 10:54 +0530, Jerin Jacob wrote:
> -Original Message-
> >
> > Date: Wed, 10 May 2017 03:16:39 -0700
> > From: Ashwin Sekhar T K
> > To: tho...@monjalon.net, jerin.ja...@caviumnetworks.com,
> > maciej.cze...@caviumnetworks.com, vikto...@rehivetech.com,
> > jianbo
On Thu, 2017-05-11 at 04:14 +, Sekhar, Ashwin wrote:
...
> > > Combining all the above comments, I made some changes on top of
> > > your
> > > patch. These changes are giving 3-4% improvement over your
> > > version.
> > >
> > > You
On Thu, 2017-05-11 at 11:16 +0800, Jianbo Liu wrote:
> Hi Ashwin,
>
> On 10 May 2017 at 23:00, Sekhar, Ashwin
> wrote:
> >
> > Hi Jianbo,
> >
> > Thanks for version v2. Addition of the prefetch instructions is
> > definitely helping performance
Hi Jianbo,
Thanks for version v2. Addition of the prefetch instructions is
definitely helping performance on ThunderX. But still performance is
slightly less than that of scalar.
I tried few small tweaks which helped improve performance on my
Thunderx setup. For details see comments inline.
On
In commit message:
s/micro/macro/
On Wed, 2017-05-10 at 10:30 +0800, Jianbo Liu wrote:
> As l3fwd_em_sse.h is renamed to l3fwd_em_sequential.h, change the
> macro
> to __L3FWD_EM_SEQUENTIAL_H__ to maintain consistency.
>
> Signed-off-by: Jianbo Liu
> ---
> examples/l3fwd/l3fwd_em_sequential.h |
On Fri, 2017-05-05 at 13:43 +0800, Jianbo Liu wrote:
> On 5 May 2017 at 12:24, Sekhar, Ashwin
> wrote:
> >
> > On Thu, 2017-05-04 at 16:42 +0800, Jianbo Liu wrote:
> > >
> > > Hi Ashwin,
> > >
> > > On 3 May 2017 at 13:24,
On Thu, 2017-05-04 at 16:42 +0800, Jianbo Liu wrote:
> Hi Ashwin,
>
> On 3 May 2017 at 13:24, Jianbo Liu wrote:
> >
> > Hi Ashwin,
> >
> > On 2 May 2017 at 19:47, Sekhar, Ashwin
> > wrote:
> > >
> > > Hi Jianbo,
> > >
>
Hi Jianbo,
I tested your neon changes on thunderx. I am seeing a performance
regression of ~10% for LPM case and ~20% for EM case with your changes.
Did you see improvement on any arm64 platform with these changes. If
yes, how much was the improvement?
FYI, I had also tried vectorizing the l3fwd
Hi,
Please find comments inline.
On Tue, 2017-05-02 at 15:14 +0800, Jianbo Liu wrote:
> Use ARM NEON intrinsics to accelerate l3 fowarding.
>
> Signed-off-by: Jianbo Liu
> ---
> examples/l3fwd/l3fwd.h | 4 -
> examples/l3fwd/l3fwd_em.c | 4 +-
> examples/l3fwd/l3fwd_em
On Tue, 2017-05-02 at 15:14 +0800, Jianbo Liu wrote:
> The l3fwd_em_sse.h is enabled by NO_HASH_LOOKUP_MULTI.
> Renaming it because it's only for single hash lookup,
> and doesn't include any x86 SSE instructions.
>
> Signed-off-by: Jianbo Liu
> ---
> examples/l3fwd/l3fwd_em.c
On Tue, 2017-05-02 at 15:59 +0800, Jianbo Liu wrote:
> On 2 May 2017 at 14:41, Jerin Jacob
> wrote:
> >
> > -Original Message-
> > >
> > > Date: Mon, 1 May 2017 22:59:53 -0700
> > > From: Ashwin Sekhar T K
> > > To: byron.mar...@intel.com, pablo.de.lara.gua...@intel.com,
> > > jerin.j
On Friday 28 April 2017 03:36 PM, Jianbo Liu wrote:
> On 27 April 2017 at 20:44, Ashwin Sekhar T K
> wrote:
>> * Added file lib/librte_efd/rte_efd_arm64.h to hold arm64
>> specific definitions
>> * Verified the changes with efd_autotest unit test case
>>
>> Signed-off-by: Ashwin Sekhar T K
>> -
Hi Jan,
Thanks for the comments. Please see my responses inline.
On Friday 28 April 2017 03:25 PM, Jan Viktorin wrote:
> Hello Ashwin Sekhar,
>
> some comments below...
>
> On Thu, 27 Apr 2017 07:10:20 -0700
> Ashwin Sekhar T K wrote:
>
>> * Added CRC compute APIs for arm64 utilizing the pmull ca
On Friday 28 April 2017 11:07 AM, Jianbo Liu wrote:
> On 28 April 2017 at 13:27, Sekhar, Ashwin wrote:
>> On Friday 28 April 2017 09:20 AM, Jianbo Liu wrote:
>>> On 27 April 2017 at 21:00, Ashwin Sekhar T K
>>> wrote:
>>>> * Enabled CONFIG_RTE_SCHED_VECTO
On Friday 28 April 2017 09:20 AM, Jianbo Liu wrote:
> On 27 April 2017 at 21:00, Ashwin Sekhar T K
> wrote:
>> * Enabled CONFIG_RTE_SCHED_VECTOR for arm64
>> * Verified the changes with sched_autotest unit test case
>>
>> Signed-off-by: Ashwin Sekhar T K
>> ---
>> config/defconfig_arm64-armv8a-l
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