[PATCH v5 3/3] riscv: override machine_args only when default

From: Sun Yuechi Support using -Dcpu_instruction_set=rv64gcv to enable V extension. Signed-off-by: Sun Yuechi --- config/riscv/meson.build | 2 ++ 1 file changed, 2 insertions(+) diff --git a/config/riscv/meson.build b/config/riscv/meson.build index e3694cf2e6..1036a86d05 100644 --- a/config/

[PATCH v5 1/3] config/riscv: detect V extension

From: Sun Yuechi This patch is derived from "config/riscv: detect presence of Zbc extension with modifications". The RISC-V C api defines architecture extension test macros These let us detect whether the V extension is supported on the compiler and -march we're building with. The C api also def

[PATCH v5 0/3] Add RISC-V V extension detection and LPM optimization

From: Sun Yuechi This patch series adds support for the RISC-V Vector (V) extension and provides an optimized implementation of `rte_lpm_lookupx4` using RVV. The initialization of vtbl_entry is not fully vectorized here because doing so would require __riscv_vluxei32_v_u32m1, which is slower tha

[PATCH v5 2/3] lib/lpm: R-V V rte_lpm_lookupx4

From: Sun Yuechi Implement LPM lookupx4 function for RISC-V architecture using RISC-V Vector Extension instruction set Signed-off-by: Sun Yuechi --- MAINTAINERS | 2 ++ lib/lpm/meson.build | 1 + lib/lpm/rte_lpm.h | 2 ++ lib/lpm/rte_lpm_rvv.h | 62 ++

[PATCH v4 2/3] lib/lpm: R-V V rte_lpm_lookupx4

From: Sun Yuechi The initialization of vtbl_entry is not fully vectorized here because doing so would require __riscv_vluxei32_v_u32m1, which is slower than the scalar approach in this small-scale scenario. - Test: app/test/lpm_perf_autotest - Platform: Banana Pi(BPI-F3) - SoC: Spacemit X60 (8 c

[PATCH v4 0/3] [PATCH v4 0/3] Add RISC-V V extension detection and LPM optimization

From: Sun Yuechi This patch series adds support for the RISC-V Vector (V) extension and provides an optimized implementation of `rte_lpm_lookupx4` using RVV. - Test: app/test/lpm_perf_autotest - Platform: Banana Pi BPI-F3 - SoC: Spacemit X60 (8 cores with Vector extension) - CPU Frequency: up t

[PATCH v4 3/3] riscv: override machine_args only when default

From: Sun Yuechi Support using -Dcpu_instruction_set=rv64gcv to enable V extension. Signed-off-by: Sun Yuechi --- config/riscv/meson.build | 2 ++ 1 file changed, 2 insertions(+) diff --git a/config/riscv/meson.build b/config/riscv/meson.build index e3694cf2e6..1036a86d05 100644 --- a/config/

[PATCH v4 1/3] config/riscv: detect V extension

From: Sun Yuechi This patch is derived from "config/riscv: detect presence of Zbc extension with modifications". The RISC-V C api defines architecture extension test macros These let us detect whether the V extension is supported on the compiler and -march we're building with. The C api also def

[PATCH v3 1/3] config/riscv: detect V extension

From: sunyuechi This patch is derived from "config/riscv: detect presence of Zbc extension with modifications". The RISC-V C api defines architecture extension test macros These let us detect whether the V extension is supported on the compiler and -march we're building with. The C api also defi

[PATCH v3 0/3] Add RISC-V V extension detection and LPM optimization

From: sunyuechi This patch series adds support for the RISC-V Vector (V) extension and provides an optimized implementation of `rte_lpm_lookupx4` using RVV. It includes runtime detection of the V extension, conditional compilation based on compiler support for RVV intrinsics. Test results using

[PATCH v3 3/3] riscv: override machine_args only when default

From: sunyuechi Support using -Dcpu_instruction_set=rv64gcv to enable V extension. Signed-off-by: sunyuechi --- config/riscv/meson.build | 2 ++ 1 file changed, 2 insertions(+) diff --git a/config/riscv/meson.build b/config/riscv/meson.build index e3694cf2e6..1036a86d05 100644 --- a/config/ri

[PATCH v3 2/3] lib/lpm: R-V V rte_lpm_lookupx4

From: sunyuechi Test results using lpm_perf_autotest on BPI-F3: scalar: 5.7 cycles rvv:2.4 cycles The best way to call this RVV function is to follow the approach used in lib/fib, where all architectures initialize a function pointer in a unified way. However, other architectures in

[PATCH v2 3/3] riscv: override machine_args only when default

From: sunyuechi Support using -Dcpu_instruction_set=rv64gcv to enable V extension. Signed-off-by: sunyuechi --- config/riscv/meson.build | 2 ++ 1 file changed, 2 insertions(+) diff --git a/config/riscv/meson.build b/config/riscv/meson.build index e3694cf2e6..1036a86d05 100644 --- a/config/ri

[PATCH v2 2/3] lib/lpm: R-V V rte_lpm_lookupx4

From: sunyuechi Test results using lpm_perf_autotest on BPI-F3: scalar: 5.7 cycles rvv:2.4 cycles The best way to call this RVV function is to follow the approach used in lib/fib, where all architectures initialize a function pointer in a unified way. However, other architectures in

[PATCH v2 0/3] Add RISC-V V extension detection and LPM optimization

From: sunyuechi This patch series adds support for the RISC-V Vector (V) extension and provides an optimized implementation of `rte_lpm_lookupx4` using RVV. It includes runtime detection of the V extension, conditional compilation based on compiler support for RVV intrinsics. Test results using

[PATCH v2 1/3] config/riscv: detect V extension

From: sunyuechi This patch is derived from "config/riscv: detect presence of Zbc extension with modifications". The RISC-V C api defines architecture extension test macros These let us detect whether the V extension is supported on the compiler and -march we're building with. The C api also defi

[PATCH v2 2/3] lib/lpm: R-V V rte_lpm_lookupx4

From: sunyuechi Test results using lpm_perf_autotest on BPI-F3: scalar: 5.7 cycles rvv:2.4 cycles The best way to call this RVV function is to follow the approach used in lib/fib, where all architectures initialize a function pointer in a unified way. However, other architectures in

[PATCH v2 3/3] riscv: override machine_args only when default

From: sunyuechi Support using -Dcpu_instruction_set=rv64gcv to enable V extension. Signed-off-by: sunyuechi --- config/riscv/meson.build | 2 ++ 1 file changed, 2 insertions(+) diff --git a/config/riscv/meson.build b/config/riscv/meson.build index e3694cf2e6..1036a86d05 100644 --- a/config/ri

[PATCH v2 2/3] lib/lpm: R-V V rte_lpm_lookupx4

From: sunyuechi Test results using lpm_perf_autotest on BPI-F3: scalar: 5.7 cycles rvv:2.4 cycles The best way to call this RVV function is to follow the approach used in lib/fib, where all architectures initialize a function pointer in a unified way. However, other architectures in

[PATCH v2 1/3] config/riscv: detect V extension

From: sunyuechi This patch is derived from "config/riscv: detect presence of Zbc extension with modifications". The RISC-V C api defines architecture extension test macros These let us detect whether the V extension is supported on the compiler and -march we're building with. The C api also defi

[PATCH v2 0/3] Add RISC-V V extension detection and LPM optimization

From: sunyuechi This patch series adds support for the RISC-V Vector (V) extension and provides an optimized implementation of `rte_lpm_lookupx4` using RVV. It includes runtime detection of the V extension, conditional compilation based on compiler support for RVV intrinsics. Test results using

[PATCH v2 3/3] riscv: override machine_args only when default

From: sunyuechi Support using -Dcpu_instruction_set=rv64gcv to enable V extension. Signed-off-by: sunyuechi --- config/riscv/meson.build | 2 ++ 1 file changed, 2 insertions(+) diff --git a/config/riscv/meson.build b/config/riscv/meson.build index e3694cf2e6..1036a86d05 100644 --- a/config/ri

[PATCH v2 1/3] config/riscv: detect V extension

From: sunyuechi This patch is derived from "config/riscv: detect presence of Zbc extension with modifications". The RISC-V C api defines architecture extension test macros These let us detect whether the V extension is supported on the compiler and -march we're building with. The C api also defi

[PATCH v2 0/3] Add RISC-V V extension detection and LPM optimization

From: sunyuechi This patch series adds support for the RISC-V Vector (V) extension and provides an optimized implementation of `rte_lpm_lookupx4` using RVV. It includes runtime detection of the V extension, conditional compilation based on compiler support for RVV intrinsics. Test results using

[PATCH 2/3] lib/lpm: R-V V rte_lpm_lookupx4

From: sunyuechi bpi-f3: scalar: 5.7 cycles rvv:2.4 cycles Maybe runtime detection in LPM should be added for all architectures, but this commit is only about the RVV part. Signed-off-by: sunyuechi --- MAINTAINERS | 2 + lib/lpm/meson.build | 1 + lib/lpm/rte_lpm.h

[PATCH 3/3] riscv: override machine_args only when default

From: sunyuechi Support using -Dcpu_instruction_set=rv64gcv to enable V extension. Signed-off-by: sunyuechi --- config/riscv/meson.build | 2 ++ 1 file changed, 2 insertions(+) diff --git a/config/riscv/meson.build b/config/riscv/meson.build index e3694cf2e6..1036a86d05 100644 --- a/config/ri

[PATCH 1/3] config/riscv: detect V extension

From: sunyuechi This patch is derived from "config/riscv: detect presence of Zbc extension with modifications". The RISC-V C api defines architecture extension test macros These let us detect whether the V extension is supported on the compiler and -march we're building with. The C api also defi

[PATCH RESEND 1/3] config/riscv: detect V extension

From: sunyuechi This patch is derived from "config/riscv: detect presence of Zbc extension with modifications". The RISC-V C api defines architecture extension test macros These let us detect whether the V extension is supported on the compiler and -march we're building with. The C api also defi

[PATCH RESEND 3/3] riscv: override machine_args only when default

From: sunyuechi Support using -Dcpu_instruction_set=rv64gcv to enable V extension. Signed-off-by: sunyuechi --- config/riscv/meson.build | 2 ++ 1 file changed, 2 insertions(+) diff --git a/config/riscv/meson.build b/config/riscv/meson.build index e3694cf2e6..1036a86d05 100644 --- a/config/ri

[PATCH RESEND 2/3] lib/lpm: R-V V rte_lpm_lookupx4

From: sunyuechi bpi-f3: scalar: 5.7 cycles rvv:2.4 cycles Maybe runtime detection in LPM should be added for all architectures, but this commit is only about the RVV part. Signed-off-by: sunyuechi --- MAINTAINERS | 2 + lib/lpm/meson.build | 1 + lib/lpm/rte_lpm.h