Currently, the indexed memory pool bitmap start address is not aligned
to cacheline size explicitly. The bitmap initialization requires the
address should be cacheline aligned. In that case, the initialization
maybe failed if the address is not cacheline aligned.
Add RTE_CACHE_LINE_ROUNDUP() to th
> -Original Message-
> From: dev On Behalf Of Suanming Mou
> Sent: Tuesday, April 28, 2020 5:14 PM
> To: Matan Azrad ; Shahaf Shuler
> ; Viacheslav Ovsiienko
>
> Cc: dev@dpdk.org; rasl...@mellanox.com; Lijian Zhang
>
> Subject: [dpdk-dev] [PATCH] net/ml
Hi,
> -Original Message-
> From: Suanming Mou
> Sent: Tuesday, April 28, 2020 12:14 PM
> To: Matan Azrad ; Shahaf Shuler
> ; Slava Ovsiienko
> Cc: dev@dpdk.org; Raslan Darawsheh ;
> lijian.zh...@arm.com
> Subject: [PATCH] net/mlx5: fix indexed pool bitmap initialization
>
> Currently, t
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