Re: [dpdk-dev] [PATCH 1/2] net/mlx5: replace memory barrier type

2017-08-24 Thread Bruce Richardson
On Thu, Aug 24, 2017 at 06:56:11AM +, Shahaf Shuler wrote: > Wednesday, August 23, 2017 4:12 PM, Bruce Richardson: > > On Wed, Aug 23, 2017 at 01:39:08PM +0200, Nélio Laranjeiro wrote: > > > On Mon, Aug 21, 2017 at 10:47:01AM +0300, Sagi Grimberg wrote: > > > > > > Acked-by: Nelio Laranjeiro >

Re: [dpdk-dev] [PATCH 1/2] net/mlx5: replace memory barrier type

2017-08-23 Thread Shahaf Shuler
Wednesday, August 23, 2017 4:12 PM, Bruce Richardson: > On Wed, Aug 23, 2017 at 01:39:08PM +0200, Nélio Laranjeiro wrote: > > On Mon, Aug 21, 2017 at 10:47:01AM +0300, Sagi Grimberg wrote: > > > > Acked-by: Nelio Laranjeiro > > > While a compiler barrier may do on platforms with strong ordering, I

Re: [dpdk-dev] [PATCH 1/2] net/mlx5: replace memory barrier type

2017-08-23 Thread Bruce Richardson
On Wed, Aug 23, 2017 at 01:39:08PM +0200, Nélio Laranjeiro wrote: > On Mon, Aug 21, 2017 at 10:47:01AM +0300, Sagi Grimberg wrote: > > From: Shahaf Shuler > > > > The reason for the requirement of a barrier between the txq writes > > and the doorbell record writes is to avoid a case where the dev

Re: [dpdk-dev] [PATCH 1/2] net/mlx5: replace memory barrier type

2017-08-23 Thread Nélio Laranjeiro
On Mon, Aug 21, 2017 at 10:47:01AM +0300, Sagi Grimberg wrote: > From: Shahaf Shuler > > The reason for the requirement of a barrier between the txq writes > and the doorbell record writes is to avoid a case where the device > reads the doorbell record's new value before the txq writes are flushe

[dpdk-dev] [PATCH 1/2] net/mlx5: replace memory barrier type

2017-08-21 Thread Sagi Grimberg
From: Shahaf Shuler The reason for the requirement of a barrier between the txq writes and the doorbell record writes is to avoid a case where the device reads the doorbell record's new value before the txq writes are flushed to memory. The current use of rte_wmb is not necessary, and can be rep