Hi Igor,
Few comments inline.
> > Subject: RE: [PATCH RFC v1 0/7] relax barriers for ENA PMD and small
> > fixes
> >
> > Hi all,
> >
> > Please see the first batch of comments related to these patches:
> >
> > 1. Relaxing the register read/write isn't always good enough.
> > Specifically
> -Original Message-
> From: Chauskin, Igor
> Sent: Thursday, April 16, 2020 9:38 PM
> To: Gavin Hu ; dev@dpdk.org
> Cc: nd ; david.march...@redhat.com;
> tho...@monjalon.net; m...@semihalf.com; Tzalik, Guy
> ; Schmeilin, Evgeny ;
> m...@semihalf.com; Honnappa Nagarahalli
> ; Ruifeng Wang
Hi all,
Please see the first batch of comments related to these patches:
1. Relaxing the register read/write isn't always good enough. Specifically,
when barriers are required between different memory types, the reordering can
occur even on x86. Yet in DPDK the io/cio/smp barrier flavors for x8
il.y...@arm.com; joyce.k...@arm.com; Bshara, Saeed
; Matushevsky, Alexander
Subject: RE: [EXTERNAL] [dpdk-dev] [PATCH RFC v1 0/7] relax barriers for ENA
PMD and small fixes
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On 3/16/2020 9:34 AM, Chauskin, Igor wrote:
> Hi Gavin,
>
> Thank you for the contribution.
> Please do not merge these changes (patches 0..7) till we (the ENA team)
> properly review and ack/nack.
Hi Igor,
Is there any progress on reviewing the set?
Thanks,
ferruh
> These changes can potenti
Hi Igor,
> -Original Message-
> From: Chauskin, Igor
> Sent: Monday, March 16, 2020 5:35 PM
> To: Gavin Hu ; dev@dpdk.org
> Cc: nd ; david.march...@redhat.com; tho...@monjalon.net;
> m...@semihalf.com; Tzalik, Guy ; Schmeilin, Evgeny
> ; m...@semihalf.com; Honnappa Nagarahalli
> ; Ruifeng
Hi Gavin,
Thank you for the contribution.
Please do not merge these changes (patches 0..7) till we (the ENA team)
properly review and ack/nack.
These changes can potentially provide performance improvement, yet we need to
ensure they are applicable for all possible scenarios. Specifically, the
To ensure the stores to the host memory are observed by NIC HW before a
door bell ring to the NIC HW and the HW starts actions, for example,
doing DMA, a barrier is required on weak memory ordering platforms, like
aarch64.
However, unnecessarily too strong barriers like 'dsb' on aarch64 will
dampe
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