antin
> ; Zhang, Tianfei ;
> Liu, Song ; Wu, Hao ;
> gaetan.ri...@6wind.com
> Subject: RE: [dpdk-dev] [PATCH v10 1/3] bus/ifpga: Add Intel FPGA BUS
> Library
>
>
>
> > -Original Message-
> > From: Xu, Rosen
> > Sent: Thursday, May 10, 2018 8:21 PM
&
; ; Zhang, Tianfei ;
> Liu, Song
> ; Wu, Hao ; gaetan.ri...@6wind.com
> Subject: RE: [dpdk-dev] [PATCH v10 1/3] bus/ifpga: Add Intel FPGA BUS Library
>
> Hi Jingjing,
>
> > -Original Message-
> > From: Wu, Jingjing
> > Sent: Thursday, May 10, 2018 16:
10/05/2018 15:51, Xu, Rosen:
> Hi Qi,
>
> I miss one comment, so I fix it in this email.
In order to avoid missing comments, and to ease reading for others,
please remove the useless context lines when replying.
> ; Zhang, Tianfei ;
> Liu, Song ; Wu, Hao ;
> gaetan.ri...@6wind.com
> Subject: RE: [dpdk-dev] [PATCH v10 1/3] bus/ifpga: Add Intel FPGA BUS Library
>
> Hi Qi,
>
> > -Original Message-
> > From: Zhang, Qi Z
> > Sent: Thursday, May 10, 2018 21:49
>
anyev, Konstantin
> ; Zhang, Tianfei ;
> Liu, Song ; Wu, Hao ;
> gaetan.ri...@6wind.com
> Subject: RE: [dpdk-dev] [PATCH v10 1/3] bus/ifpga: Add Intel FPGA BUS Library
>
> Hi Qi,
>
> I miss one comment, so I fix it in this email.
>
> > -Original Message-
> &
antin
> ; Zhang, Tianfei ;
> Liu, Song ; Wu, Hao ;
> gaetan.ri...@6wind.com
> Subject: RE: [dpdk-dev] [PATCH v10 1/3] bus/ifpga: Add Intel FPGA BUS
> Library
>
>
>
> > -Original Message-
> > From: Xu, Rosen
> > Sent: Thursday, May 10, 2018 9:29 PM
lan
> ; Richardson, Bruce
> ; shreyansh.j...@nxp.com; Yigit, Ferruh
> ; Ananyev, Konstantin
> ; Zhang, Tianfei ;
> Liu, Song ; Wu, Hao ;
> gaetan.ri...@6wind.com
> Subject: Re: [dpdk-dev] [PATCH v10 1/3] bus/ifpga: Add Intel FPGA BUS
> Library
>
> Hi Qi,
>
> >
> ; Zhang, Tianfei ;
> Liu, Song ; Wu, Hao ;
> gaetan.ri...@6wind.com
> Subject: RE: [dpdk-dev] [PATCH v10 1/3] bus/ifpga: Add Intel FPGA BUS Library
>
> Hi Qi,
>
> > -Original Message-
> > From: Zhang, Qi Z
> > Sent: Thursday, May 10, 2018 20:27
ev, Konstantin
> ; Zhang, Tianfei ;
> Liu, Song ; Wu, Hao ;
> gaetan.ri...@6wind.com
> Subject: RE: [dpdk-dev] [PATCH v10 1/3] bus/ifpga: Add Intel FPGA BUS
> Library
>
> Hi Rosen:
>
> > -Original Message-
> > From: dev [mailto:dev-boun...@dpdk.org] On
j...@nxp.com;
> Yigit, Ferruh ; Ananyev, Konstantin
> ; Zhang, Tianfei ;
> Liu, Song ; Wu, Hao ;
> gaetan.ri...@6wind.com
> Subject: [dpdk-dev] [PATCH v10 1/3] bus/ifpga: Add Intel FPGA BUS Library
>
> From: Rosen Xu
>
> Defined FPGA-BUS for Acceleration Drivers of AFUs
&
uh ; Ananyev, Konstantin
> ; Zhang, Tianfei ;
> Liu, Song ; Wu, Hao ;
> gaetan.ri...@6wind.com
> Subject: RE: [dpdk-dev] [PATCH v10 1/3] bus/ifpga: Add Intel FPGA BUS
> Library
>
> Hi, Rosen
>
> Few comments below.
Thanks a lot Jingjing.
>
> Thanks
>
Hi, Rosen
Few comments below.
Thanks
Jingjing
[..]
> +static struct rte_ifpga_device *
> +ifpga_find_ifpga_dev(const struct rte_rawdev *rdev)
> +{
> + struct rte_ifpga_device *ifpga_dev = NULL;
> +
> + TAILQ_FOREACH(ifpga_dev, &ifpga_device_list, next) {
> + if (rdev &&
From: Rosen Xu
Defined FPGA-BUS for Acceleration Drivers of AFUs
1. FPGA PCI Scan (1st Scan) follows DPDK UIO/VFIO PCI Scan Process,
probe Intel FPGA Rawdev Driver, it will be covered in following patches.
2. AFU Scan(2nd Scan) bind DPDK driver to FPGA Partial-Bitstream.
This scan is trigged by
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