.com; jer...@marvell.com; Pavan Nikhilesh
> ; Honnappa Nagarahalli
> ; Ruifeng Wang
> ; Phil Yang ; Joyce Kong
> ; Steve Capper
> Subject: Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: relax the io barrier for
> aarch64
>
> On Fri, Jan 3, 2020 at 12:00 PM
n.net;
> > rasl...@mellanox.com; maxime.coque...@redhat.com; tiwei@intel.com;
> > hemant.agra...@nxp.com; jer...@marvell.com; Pavan Nikhilesh
> > ; Honnappa Nagarahalli
> > ; Ruifeng Wang
> > ; Phil Yang ; Joyce Kong
> > ; Steve Capper
> > Subject: Re: [
.com; jer...@marvell.com; Pavan Nikhilesh
> ; Honnappa Nagarahalli
> ; Ruifeng Wang
> ; Phil Yang ; Joyce Kong
> ; Steve Capper
> Subject: Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: relax the io barrier for
> aarch64
>
> On Mon, Dec 23, 2019 at 3:46 PM Gavin Hu wrote:
&
n.net;
> > rasl...@mellanox.com; maxime.coque...@redhat.com;
> > tiwei@intel.com; hemant.agra...@nxp.com; jer...@marvell.com;
> > Pavan Nikhilesh ; Honnappa Nagarahalli
> > ; Ruifeng Wang
> > ; Phil Yang ; Joyce Kong
> > ; Steve Capper
> > Subject: Re: [dpdk-dev
.com; jer...@marvell.com;
> Pavan Nikhilesh ; Honnappa Nagarahalli
> ; Ruifeng Wang
> ; Phil Yang ; Joyce Kong
> ; Steve Capper
> Subject: Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: relax the io barrier for
> aarch64
>
> On Mon, Dec 23, 2019 at 2:44 PM Gavin Hu wrote:
> &
On Mon, Dec 23, 2019 at 2:44 PM Gavin Hu wrote:
>
> Hi Jerin,
Hi Gavin,
>
> I think we are on the same page with regard to the problem, and the
> situations, thanks for illuminating the historical background of the two
> barriers.
> About the solution, I added inline comments.
> > It will be o
Phil Yang ; Joyce Kong
> ; Steve Capper
> Subject: Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: relax the io barrier for
> aarch64
>
> On Fri, Dec 20, 2019 at 12:02 PM Gavin Hu wrote:
> >
> > Hi Jerin,
>
> Hi Gavin,
>
>
> > > > > > >
> &
On Fri, Dec 20, 2019 at 12:02 PM Gavin Hu wrote:
>
> Hi Jerin,
Hi Gavin,
> > > > > >
> > > > > > The peripheral coherence order for a memory-mapped peripheral
> > > > signifies the
> > > > > > order in which accesses arrive at the endpoint. For a read or a
> > > > > > write
> > > > RW1
> > >
ant.agra...@nxp.com; jer...@marvell.com;
> Pavan Nikhilesh ; Honnappa Nagarahalli
> ; Ruifeng Wang
> ; Phil Yang ; Joyce Kong
> ; Steve Capper
> Subject: Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: relax the io barrier for
> aarch64
>
> On Fri, Dec 20, 2019 at 9:49 AM Gavin Hu wrote:
>
Marchand
> > ; tho...@monjalon.net;
> > rasl...@mellanox.com; maxime.coque...@redhat.com;
> > tiwei@intel.com; hemant.agra...@nxp.com; jer...@marvell.com;
> > Pavan Nikhilesh ; Honnappa Nagarahalli
> > ; Ruifeng Wang
> > ; Phil Yang ; Joyce Kong
> > ; S
> tiwei@intel.com; hemant.agra...@nxp.com; jer...@marvell.com;
> Pavan Nikhilesh ; Honnappa Nagarahalli
> ; Ruifeng Wang
> ; Phil Yang ; Joyce Kong
> ; Steve Capper
> Subject: Re: [dpdk-dev] [PATCH v2 1/3] eal/arm64: relax the io barrier for
> aarch64
>
> On Fri, Dec 20,
On Fri, Dec 20, 2019 at 9:03 AM Jerin Jacob wrote:
>
> On Fri, Dec 20, 2019 at 8:40 AM Gavin Hu wrote:
> >
> > Armv8's peripheral coherence order is a total order on all reads and writes
> > to that peripheral.[1]
> >
> > The peripheral coherence order for a memory-mapped peripheral signifies the
On Fri, Dec 20, 2019 at 8:40 AM Gavin Hu wrote:
>
> Armv8's peripheral coherence order is a total order on all reads and writes
> to that peripheral.[1]
>
> The peripheral coherence order for a memory-mapped peripheral signifies the
> order in which accesses arrive at the endpoint. For a read or
Armv8's peripheral coherence order is a total order on all reads and writes
to that peripheral.[1]
The peripheral coherence order for a memory-mapped peripheral signifies the
order in which accesses arrive at the endpoint. For a read or a write RW1
and a read or a write RW2 to the same peripheral
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