From: Kiran Kumar K <kirankum...@marvell.com>
Adding support to configure NPC on device initialization. This involves
reading the MKEX and initializing the necessary data.
Signed-off-by: Kiran Kumar K <kirankum...@marvell.com>
---
drivers/net/cnxk/cnxk_ethdev.c | 25 ++++++++++++++++++++++---
drivers/net/cnxk/cnxk_ethdev.h | 3 +++
drivers/net/cnxk/cnxk_ethdev_devargs.c | 3 +++
3 files changed, 28 insertions(+), 3 deletions(-)
diff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c
index f2df0ba..d1a7f2e 100644
--- a/drivers/net/cnxk/cnxk_ethdev.c
+++ b/drivers/net/cnxk/cnxk_ethdev.c
@@ -8,7 +8,8 @@ nix_get_rx_offload_capa(struct cnxk_eth_dev *dev)
{
uint64_t capa = CNXK_NIX_RX_OFFLOAD_CAPA;
- if (roc_nix_is_vf_or_sdp(&dev->nix))
+ if (roc_nix_is_vf_or_sdp(&dev->nix) ||
+ dev->npc.switch_header_type == ROC_PRIV_FLAGS_HIGIG)
capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
return capa;
@@ -120,6 +121,7 @@ nix_update_flow_ctrl_config(struct rte_eth_dev *eth_dev)
/* To avoid Link credit deadlock on Ax, disable Tx FC if it's enabled */
if (roc_model_is_cn96_Ax() &&
+ dev->npc.switch_header_type != ROC_PRIV_FLAGS_HIGIG &&
(fc_cfg.mode == RTE_FC_FULL || fc_cfg.mode == RTE_FC_RX_PAUSE)) {
fc_cfg.mode =
(fc_cfg.mode == RTE_FC_FULL ||
@@ -419,8 +421,10 @@ cnxk_rss_ethdev_to_nix(struct cnxk_eth_dev *dev, uint64_t
ethdev_rss,
dev->ethdev_rss_hf = ethdev_rss;
- if (ethdev_rss & ETH_RSS_L2_PAYLOAD)
+ if (ethdev_rss & ETH_RSS_L2_PAYLOAD &&
+ dev->npc.switch_header_type == ROC_PRIV_FLAGS_LEN_90B) {
flowkey_cfg |= FLOW_KEY_TYPE_CH_LEN_90B;
+ }
if (ethdev_rss & ETH_RSS_C_VLAN)
flowkey_cfg |= FLOW_KEY_TYPE_VLAN;
@@ -837,11 +841,18 @@ cnxk_nix_configure(struct rte_eth_dev *eth_dev)
roc_nix_err_intr_ena_dis(nix, true);
roc_nix_ras_intr_ena_dis(nix, true);
- if (nix->rx_ptp_ena) {
+ if (nix->rx_ptp_ena &&
+ dev->npc.switch_header_type == ROC_PRIV_FLAGS_HIGIG) {
plt_err("Both PTP and switch header enabled");
goto free_nix_lf;
}
+ rc = roc_nix_switch_hdr_set(nix, dev->npc.switch_header_type);
+ if (rc) {
+ plt_err("Failed to enable switch type nix_lf rc=%d", rc);
+ goto free_nix_lf;
+ }
+
/* Setup LSO if needed */
rc = nix_lso_fmt_setup(dev);
if (rc) {
@@ -1293,6 +1304,11 @@ cnxk_eth_dev_init(struct rte_eth_dev *eth_dev)
dev->speed_capa = nix_get_speed_capa(dev);
/* Initialize roc npc */
+ dev->npc.roc_nix = nix;
+ rc = roc_npc_init(&dev->npc);
+ if (rc)
+ goto free_mac_addrs;
+
plt_nix_dbg("Port=%d pf=%d vf=%d ver=%s hwcap=0x%" PRIx64
" rxoffload_capa=0x%" PRIx64 " txoffload_capa=0x%" PRIx64,
eth_dev->data->port_id, roc_nix_get_pf(nix),
@@ -1326,6 +1342,9 @@ cnxk_eth_dev_uninit(struct rte_eth_dev *eth_dev, bool
reset)
roc_nix_npc_rx_ena_dis(nix, false);
+ /* Disable and free rte_flow entries */
+ roc_npc_fini(&dev->npc);
+
/* Disable link status events */
roc_nix_mac_link_event_start_stop(nix, false);
diff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h
index 1c4403c..4879ef9 100644
--- a/drivers/net/cnxk/cnxk_ethdev.h
+++ b/drivers/net/cnxk/cnxk_ethdev.h
@@ -133,6 +133,9 @@ struct cnxk_eth_dev {
/* ROC NIX */
struct roc_nix nix;
+ /* ROC NPC */
+ struct roc_npc npc;
+
/* ROC RQs, SQs and CQs */
struct roc_nix_rq *rqs;
struct roc_nix_sq *sqs;
diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c
b/drivers/net/cnxk/cnxk_ethdev_devargs.c
index 4af2803..7fd06eb 100644
--- a/drivers/net/cnxk/cnxk_ethdev_devargs.c
+++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c
@@ -150,6 +150,9 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs,
struct cnxk_eth_dev *dev)
dev->nix.rss_tag_as_xor = !!rss_tag_as_xor;
dev->nix.max_sqb_count = sqb_count;
dev->nix.reta_sz = reta_sz;
+ dev->npc.flow_prealloc_size = flow_prealloc_size;
+ dev->npc.flow_max_priority = flow_max_priority;
+ dev->npc.switch_header_type = switch_header_type;
return 0;
exit:
--
2.8.4
