> -----Original Message-----
> From: Dariusz Sosnowski <dsosnow...@nvidia.com>
> Sent: Monday, September 19, 2022 19:37
> To: Matan Azrad <ma...@nvidia.com>; Slava Ovsiienko <viachesl...@nvidia.com>
> Cc: dev@dpdk.org
> Subject: [PATCH 2/7] common/mlx5: add hairpin SQ buffer type capabilities
>
> This patch extends HCA_CAP and SQ Context structs available in PRM. This
> fields allow checking if NIC supports storing hairpin SQ's WQ buffer in host
> memory and configuring such memory placement.
>
> HCA capabilities are extended with the following fields:
>
> - hairpin_sq_wq_in_host_mem - If set, then NIC supports using host memory as
> a backing storage for hairpin SQ's WQ buffer.
> - hairpin_sq_wqe_bb_size - Indicates the required size of SQ WQE basic
> block.
>
> SQ Context is extended with hairpin_wq_buffer_type which informs NIC where
> SQ's WQ buffer will be stored. This field can take the following values:
>
> - MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_INTERNAL_BUFFER - WQ buffer will be
> stored in unlocked device memory.
> - MLX5_SQC_HAIRPIN_WQ_BUFFER_TYPE_HOST_MEMORY - WQ buffer will be stored
> in host memory. Buffer is provided by PMD.
>
> Signed-off-by: Dariusz Sosnowski <dsosnow...@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viachesl...@nvidia.com>
