Thanks yf! I believe T-Head C908 and other C9xx RISC-V Cores will need the T-Head Errata for Strongly-Ordered Memory Type, according to this Linux Patch:
https://patchwork.kernel.org/project/linux-riscv/patch/20210911092139.79607-3-guo...@kernel.org/#24450685 The post suggests that T-Head will switch to the new RISC-V Svpbmt Extension for newer RISC-V Cores. But I don't believe Svpbmt is used by any RISC-V Core yet. Lup On Mon, Dec 11, 2023 at 8:30 PM yfliu2008 <yfliu2...@qq.com.invalid> wrote: > Congratulations! > > > Do you know if T-Head C908 needs the errata? > > > > Regards, > yf > > > > > Original > > > > From:"Lee, Lup Yuen"< lu...@appkaki.com >; > > Date:2023/12/10 7:11 > > To:"dev"< dev@nuttx.apache.org >; > > Subject:[Article] NuttX on Ox64 BL808 RISC-V SBC: Fixed the UART > Interruptand Platform-Level Interrupt Controller > > > Last week we walked through the Serial Console for Pine64 Ox64 BL808 64-bit > RISC-V Single-Board Computer. And we hit some illogical impossible problems > on NuttX for Ox64: > > (1) Console Input is always empty. (Can’t enter any Console Commands) > (2) Interrupt Claim is forever 0. (Ox64 won’t tell us which Interrupt was > fired!) > (3) Leaky Writes are mushing up adjacent Interrupt Registers. (Or maybe > Leaky Reads?) > > Today we discover the One Single Culprit behind all this rowdy mischief: > Weak Ordering in the MMU! (Memory Management Unit) > > Here’s how we solved the baffling mystery: > https://lupyuen.codeberg.page/articles/plic3.html > > Lup
