The branch stable/13 has been updated by np:
URL:
https://cgit.FreeBSD.org/src/commit/?id=0c65e339d8c74020024c276f8e9532e549085725
commit 0c65e339d8c74020024c276f8e9532e549085725
Author: Navdeep Parhar <n...@freebsd.org>
AuthorDate: 2021-06-01 19:57:53 +0000
Commit: Navdeep Parhar <n...@freebsd.org>
CommitDate: 2021-10-20 17:32:18 +0000
cxgbe/iw_cxgbe: Support for 512 SGL entries in one memory registration.
Use the correct SGL limit within iw_cxgbe, firmwares >= 1.25.6.0 support
upto 512 entries per MR.
Obtained from: Chelsio Communications
Sponsored by: Chelsio Communications
(cherry picked from commit 211972cfb816f8da8b8a4c524b44dde4638c3288)
---
sys/dev/cxgbe/iw_cxgbe/iw_cxgbe.h | 8 ++++++++
sys/dev/cxgbe/iw_cxgbe/mem.c | 3 +--
sys/dev/cxgbe/iw_cxgbe/provider.c | 3 +--
sys/dev/cxgbe/iw_cxgbe/qp.c | 2 +-
sys/dev/cxgbe/iw_cxgbe/t4.h | 7 ++-----
5 files changed, 13 insertions(+), 10 deletions(-)
diff --git a/sys/dev/cxgbe/iw_cxgbe/iw_cxgbe.h
b/sys/dev/cxgbe/iw_cxgbe/iw_cxgbe.h
index 1a717d6352c8..59ca38a96004 100644
--- a/sys/dev/cxgbe/iw_cxgbe/iw_cxgbe.h
+++ b/sys/dev/cxgbe/iw_cxgbe/iw_cxgbe.h
@@ -178,6 +178,14 @@ static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
return (int)(rdev->adap->vres.stag.size >> 5);
}
+static inline int t4_max_fr_depth(struct c4iw_rdev *rdev, bool use_dsgl)
+{
+ if (rdev->adap->params.ulptx_memwrite_dsgl && use_dsgl)
+ return rdev->adap->params.dev_512sgl_mr ?
T4_MAX_FR_FW_DSGL_DEPTH : T4_MAX_FR_DSGL_DEPTH;
+ else
+ return T4_MAX_FR_IMMD_DEPTH;
+}
+
#define C4IW_WR_TO (60*HZ)
struct c4iw_wr_wait {
diff --git a/sys/dev/cxgbe/iw_cxgbe/mem.c b/sys/dev/cxgbe/iw_cxgbe/mem.c
index 3f016c0cc0c1..dab812d58eec 100644
--- a/sys/dev/cxgbe/iw_cxgbe/mem.c
+++ b/sys/dev/cxgbe/iw_cxgbe/mem.c
@@ -624,8 +624,7 @@ struct ib_mr *c4iw_alloc_mr(struct ib_pd *pd,
rhp = php->rhp;
if (mr_type != IB_MR_TYPE_MEM_REG ||
- max_num_sg > t4_max_fr_depth(
- rhp->rdev.adap->params.ulptx_memwrite_dsgl && use_dsgl))
+ max_num_sg > t4_max_fr_depth(&rhp->rdev, use_dsgl))
return ERR_PTR(-EINVAL);
mhp = kzalloc(sizeof(*mhp), GFP_KERNEL);
diff --git a/sys/dev/cxgbe/iw_cxgbe/provider.c
b/sys/dev/cxgbe/iw_cxgbe/provider.c
index 53106073d101..02a32fa4c1fc 100644
--- a/sys/dev/cxgbe/iw_cxgbe/provider.c
+++ b/sys/dev/cxgbe/iw_cxgbe/provider.c
@@ -348,8 +348,7 @@ c4iw_query_device(struct ib_device *ibdev, struct
ib_device_attr *props,
props->max_mr = c4iw_num_stags(&dev->rdev);
props->max_pd = T4_MAX_NUM_PD;
props->local_ca_ack_delay = 0;
- props->max_fast_reg_page_list_len =
- t4_max_fr_depth(sc->params.ulptx_memwrite_dsgl && use_dsgl);
+ props->max_fast_reg_page_list_len = t4_max_fr_depth(&dev->rdev,
use_dsgl);
return (0);
}
diff --git a/sys/dev/cxgbe/iw_cxgbe/qp.c b/sys/dev/cxgbe/iw_cxgbe/qp.c
index eb314a6034c8..c1006109762c 100644
--- a/sys/dev/cxgbe/iw_cxgbe/qp.c
+++ b/sys/dev/cxgbe/iw_cxgbe/qp.c
@@ -714,7 +714,7 @@ static int build_memreg(struct t4_sq *sq, union t4_wr *wqe,
int pbllen = roundup(mhp->mpl_len * sizeof(u64), 32);
int rem;
- if (mhp->mpl_len > t4_max_fr_depth(use_dsgl && dsgl_supported))
+ if (mhp->mpl_len > t4_max_fr_depth(&mhp->rhp->rdev, use_dsgl))
return -EINVAL;
if (wr->mr->page_size > C4IW_MAX_PAGE_SIZE)
return -EINVAL;
diff --git a/sys/dev/cxgbe/iw_cxgbe/t4.h b/sys/dev/cxgbe/iw_cxgbe/t4.h
index 70385b4ff6b6..88e7d6418615 100644
--- a/sys/dev/cxgbe/iw_cxgbe/t4.h
+++ b/sys/dev/cxgbe/iw_cxgbe/t4.h
@@ -103,11 +103,8 @@ struct t4_status_page {
#define T4_MAX_FR_IMMD_DEPTH (T4_MAX_FR_IMMD / sizeof(u64))
#define T4_MAX_FR_DSGL 1024
#define T4_MAX_FR_DSGL_DEPTH (T4_MAX_FR_DSGL / sizeof(u64))
-
-static inline int t4_max_fr_depth(int use_dsgl)
-{
- return use_dsgl ? T4_MAX_FR_DSGL_DEPTH : T4_MAX_FR_IMMD_DEPTH;
-}
+#define T4_MAX_FR_FW_DSGL 4096
+#define T4_MAX_FR_FW_DSGL_DEPTH (T4_MAX_FR_FW_DSGL / sizeof(u64))
#define T4_RQ_NUM_SLOTS 2
#define T4_RQ_NUM_BYTES (T4_EQ_ENTRY_SIZE * T4_RQ_NUM_SLOTS)
