Reviewed-by: Hao A Wu
Best Regards,
Hao Wu
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of
> ian.c...@intel.com
> Sent: Thursday, June 23, 2022 2:22 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Ian ; Huang, Jenny ;
> Shih, More ; Wu, Hao A ; Ni,
> Ray
> Subject: [edk2-devel
From: Ian Chiu
Add support process Port Speed field value of PORTSC according to
Supported Protocol Capability (define in xHCI spec 1.1)
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3914
The value of Port Speed field in PORTSC bit[10:13]
(xHCI spec 1.1 section 5.4.8) should be change to
Hello everyone, Thanks for the helpful answers.
After discussion with the mentors, it was decided that we should first
get the Rust std to work in DXE phase. So for now, that is the goal.
Once DXE is complete and there is still time left (or I can just do it
after GSoC as well), then I might look
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3915
This commit adds a definition type 7 Platform Capabilities Structure
and the struct definition for NFIT Table Structure Types.
The type has been added since ACPI Specification Version 6.2A.
Signed-off-by: Miki Shindo
Cc: Michael D Kinney
Fix a typo below:
blocking I/O request will wait for all the (synchronous -> asynchronous) I/O
requests to complete first before sending down the synchronous request
Best Regards,
Hao Wu
> -Original Message-
> From: Wu, Hao A
> Sent: Thursday, June 23, 2022 10:47 AM
> To: devel@edk2.grou
Hello,
Several concerns:
1. Raising the TPL to NOTIFY level for blocking/synchronous BlockIO service
will break the using case when the co-existence of synchronous and
non-blocking/asynchronous IO tasks
As far as I know, in DiskIoDxe, blocking I/O request will wait for all the
synchronous I/O r
On June 22, 2022 5:23 PM, Gerd Hoffmann wrote:
>
> > Yes, PlatformReserveEmuVariableNvStore() will be a separated function
> > and it returns the pointer of the allocated storage. Then this pointer
> > can be set to either the PCD (PlatformPei) or in PlatformInfoHob
> > (PeilessStartupLib).
>
> I
Reviewed-by: Ray Ni
> -Original Message-
> From: Taylor Beebe
> Sent: Thursday, June 16, 2022 5:23 AM
> To: devel@edk2.groups.io
> Cc: Dong, Eric ; Ni, Ray ; Kumar,
> Rahul1
> Subject: [PATCH v1 1/1] UefiCpuPkg: CpuDxe: Set RW and P Attributes on Split
> Pages
>
> From: Taylor Beebe
Reviewed-by: Hao A Wu
A couple of minor modifications will be done during merging:
1) " XHCI 1.1 spec November 2019" -> " XHCI 1.1 spec November 2017";
2) Space indent refine according to the uncrustify tool report.
Best Regards,
Hao Wu
> -Original Message-
> From: Chiu, Ian
> Sent: We
I agree with other comments here. I mainly want to add that if you're
new to PI/UEFI, you might find the following resource helpful for tying
together some pieces from the code and documents like the PI Spec.
https://github.com/tianocore-docs/Docs/raw/master/White_Papers/A_Tour_Beyond_BIOS_Memo
Hi Ayush,
For your work to make Rust run in PEI I would recommend writing a generic heap
manager that uses the PEI services AllocatePage() and FreePage(). PEI does
allow you to truly free up memory but only when allocated in 4KB increments.
Your heap manager can allow the Rust program to go to
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3951
Add CONNECT HTTP command in order to create a tunnel from HTTPS
Proxy Server to EndPoint Server.
Add support to connect through proxy server using DevicePath
sent to the Boot Manager.
Cc: Maciej Rabeda
Cc: Wu Jiaxin
Cc: Siyuan Fu
Cc: Jian
Andrew,
Yes, adding a new HOB type to represent free pool would probably be the
easiest.
Or we could write or borrow a traditional malloc() implementation,
similar to DXE's pool allocator, and back it with memory from
AllocatePages(). That would probably have better performance, and would
There's a lot of major pending changes I'm aware of in the variable
stack. At least:
1. "Variable Protection" - Extensions for encryption and replay protection
https://github.com/judahvang/edk2/tree/rpmc-update
2. "Storage Agnostic Variables / UEFI Variable Router"
https://github.com/makubacki/
Brian,
I think all the PEI Allocate Pool does is make a HOB [1]. I don’t think we can
remove HOBs when memory is freed as that would change pointers to pool. It may
be possible to mark a region as free and allocate from that list batch 1st, and
just over allocate space if needed. It could be a
I’m guessing all the CI testing is on Python 3.8.x
I noticed one of the CI pipes is asking for Python 3.8 [1]
[1]
https://github.com/tianocore/edk2/blob/master/.azurepipelines/Ubuntu-PatchCheck.yml
Thanks,
Andrew Fish
> On Jun 22, 2022, at 7:34 AM, Andrew (EFI) Fish wrote:
>
> That looks l
Nate,
FWIW I welcome having a standard interface to write EFI variables in
PEI. Not all platforms store variables in flash, so they don't all have
tricky issues with fault-tolerant writes to h/w which is also being used
for code fetches. And writing variables early makes it possible to
modi
Sorry for the late response to this thread...
PEI has grown greatly in complexity, as Andrew pointed out. Do we
(TianoCore community) think it's time to add a real pool manager to
PEI? There's getting to be quite a bit of post-DRAM-initialization PEI
code on some platforms. And really, havin
This appears to be mostly redundant with
MinPlatformPkg\Library\SerialPortTerminalLib.
The only feature my implementation has the current one does not is the ability
to change the terminal type. I'll add that feature to the existing library and
remove this patch from the series.
Thanks,
Nate
> On Jun 22, 2022, at 10:43 AM, Marvin Häuser wrote:
>
> Hey Andrew,
>
> thanks for verifying! If my last mail was not clear, this is already done for
> IA32 builds, by the way. I suspect more trouble appeared there due to the
> lack of IP-relative addressing.
>
I though the issue was on
On Wed, 22 Jun 2022 at 17:38, Thomas Abraham wrote:
>
> For Arm platforms that support more that one serial port, one of the
> serial port can be used for connecting debuggers such as WinDbg. There
> are PCDs that allow the base address and clock rate to be specified for
> this debug serial port b
I reached out to the Xcode ld64 maintainer to make sure it is safe to use
-read_only_relocs suppress this way.
Thanks,
Andrew Fish
> On Jun 18, 2022, at 8:19 PM, Andrew Fish via groups.io
> wrote:
>
> Marvin,
>
> I’ll look into this.
>
> The history here is the original ld64 flags are wha
On 22/06/2022 15:52, Ard Biesheuvel wrote:
On Wed, 22 Jun 2022 at 12:12, Thomas Abraham wrote:
Add a PCD to specify the interrupt number of the serial debug port
controller.
Why do we need this?
The commit message will be updated in next version of this patch the
describes the need fo
For Arm platforms that support more that one serial port, one of the
serial port can be used for connecting debuggers such as WinDbg. There
are PCDs that allow the base address and clock rate to be specified for
this debug serial port but not its interrupt number. So add a PCD to
specify the interr
On Thu, 16 Jun 2022 at 14:56, Gerd Hoffmann wrote:
>
> We can have multiple [LibraryClasses] sections, so we can place
> all TPM-related library configuration to a single include file.
>
> Signed-off-by: Gerd Hoffmann
Reviewed-by: Ard Biesheuvel
Merged as #3000,
> ---
> OvmfPkg/OvmfTpmLibs
On Tue, 21 Jun 2022 at 23:28, Nicolas Ojeda Leon wrote:
>
> Increased control is provided in Ovmf platforms to define and configure
> the specifications of multiple PCI host bridges in the hypervisor. The
> host propagates this information to the guest, initially through fw-cfg
> interface.
>
> In
On Sat, 18 Jun 2022 at 04:45, Rebecca Cran wrote:
>
> It looks like this hasn't been pushed. Could someone commit/push it please?
>
Merged as #2999
>
> --
>
> Rebecca Cran
>
>
> On 5/16/22 10:26, Sami Mujawar wrote:
> > Hi Rebecca,
> >
> > Thank you for this patch.
> > These changes look good t
On Wed, 22 Jun 2022 at 12:12, Thomas Abraham wrote:
>
> Add a PCD to specify the interrupt number of the serial debug port
> controller.
>
Why do we need this?
> Signed-off-by: Thomas Abraham
> Change-Id: I4ce6d29cdf5e8b5fcbfe740269d966a53f2b852a
Please drop the change id
> ---
> ArmPlatform
On Wed, 22 Jun 2022 at 14:10, Thomas Abraham wrote:
>
>
>
> On 22/06/2022 12:56, Rohit Mathew via groups.io wrote:
> > Changes since V1:
> > - Rebased on top of latest master branch.
> > - Updated copyright and date.
> >
> > Changes since V2:
> > - Addressed comments from Thomas.
> >
> > This patc
That looks like an issue with using Python 3.9 as it changed tostring to
tobyte.
> On Jun 22, 2022, at 7:25 AM, Shivraj Patil wrote:
>
>
> Hello,
> I am observing the following failure while trying to build Aurora
> AU_LINUX_EMBEDDED_LE.PRODUCT.1.0_TARGET_ALL.01.318.215. Please have a look
Hello,
I am observing the following failure while trying to build Aurora
AU_LINUX_EMBEDDED_LE.PRODUCT.1.0_TARGET_ALL.01.318.215. Please have a look and
provide a solution for the same.
(Python 3.9.4 on linux) Traceback (most recent call last):
| File
"/local/mnt3/workspace3/shivpati/Aurora/bu
Hi,
While building images for LE.UM.7.4.1 , AU tag-
AU_LINUX_EMBEDDED_LE.UM.7.4.1_TARGET_ALL.01.394.080 the build was failing.
Please find the trace below:
| build.py...
| : error C0DE: Unknown fatal error when processing
[/local/mnt/workspace/PAL/7.4.1/build-qti-distro-nogplv3-debug/tmp-glib
On 22/06/2022 12:56, Rohit Mathew via groups.io wrote:
Changes since V1:
- Rebased on top of latest master branch.
- Updated copyright and date.
Changes since V2:
- Addressed comments from Thomas.
This patch series aims at routing uart logs via different sets of uart ports,
namely secure por
Hi Thomas,
I have addressed the comments in V3.
On Mon, Jun 20, 2022 at 06:29 PM, Thomas Abraham wrote:
>
> Hi Rohit,
>
> On 20/06/2022 16:25, Rohit Mathew via groups.io wrote:
>
>> Route secure (from secure partition) and non-secure console messages
>> to different sets of UART console ports
Route secure (from secure partition) and non-secure console messages
to different sets of UART console ports. This aligns with the security
state the PE is in when logs are put out. In addition, this allows
consolidation of UART related macros across all the variants of
Neoverse reference design pl
Changes since V1:
- Rebased on top of latest master branch.
- Updated copyright and date.
Changes since V2:
- Addressed comments from Thomas.
This patch series aims at routing uart logs via different sets of uart ports,
namely secure port for secure partition logs and non-secure port for all othe
Remove redundant platform descriptions (descriptions which are already
part of SSDT) from DSDT for SGI-575 platform.
Signed-off-by: Rohit Mathew
---
Platform/ARM/SgiPkg/AcpiTables/Sgi575/Dsdt.asl | 66 +---
1 file changed, 1 insertion(+), 65 deletions(-)
diff --git a/Platform/AR
From: Ian Chiu
Add support process Port Speed field value of PORTSC according to
Supported Protocol Capability (define in xHCI spec 1.1)
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3914
The value of Port Speed field in PORTSC bit[10:13]
(xHCI spec 1.1 section 5.4.8) should be change to
Add a PCD to specify the interrupt number of the serial debug port
controller.
Signed-off-by: Thomas Abraham
Change-Id: I4ce6d29cdf5e8b5fcbfe740269d966a53f2b852a
---
ArmPlatformPkg/ArmPlatformPkg.dec | 1 +
1 file changed, 1 insertion(+)
diff --git a/ArmPlatformPkg/ArmPlatformPkg.dec
b/ArmPlat
> > Copying over the content in PlatformInitLib makes sense too, probably best
> > as separate function.
> Yes, PlatformReserveEmuVariableNvStore() will be a separated function
> and it returns the pointer of the allocated storage. Then this pointer
> can be set to either the PCD (PlatformPei) or
On June 22, 2022 3:01 PM, Gerd Hoffmann wrote:
> On Wed, Jun 22, 2022 at 02:02:00AM +, Xu, Min M wrote:
> > On June 20, 2022 7:01 PM, Gerd Hoffman wrote:
> > >
> > > There is PcdEmuVariableNvStoreReserved for that. How about just
> > > copying the store to ram, then set PcdEmuVariableNvStoreRe
On Wed, Jun 22, 2022 at 02:02:00AM +, Xu, Min M wrote:
> On June 20, 2022 7:01 PM, Gerd Hoffman wrote:
> >
> > There is PcdEmuVariableNvStoreReserved for that. How about just copying
> > the store to ram, then set PcdEmuVariableNvStoreReserved to the location
> > and let the existing logic ha
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