Reviewed-by: Zhiguang Liu
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Ni, Ray
> Sent: Wednesday, May 24, 2023 8:29 PM
> To: devel@edk2.groups.io
> Subject: [edk2-devel] [PATCH 0/6] Fine tune SimicsOpenBoardPkg
>
>
> Ray Ni (6):
> SimicsOpenBoardPkg: Remove un-used
Thanks, Ray. Looking forward to seeing the ideas on this feature!
Regards,
Kun
On 5/24/2023 5:46 PM, Ni, Ray wrote:
Kun,
Thanks for raising that up😊
We have some ideas. Will post them later.
Looking forward to work with community together.
Thanks,
Ray
-Original Message-
From: Kun Qi
[AMD Official Use Only - General]
Hi Abdul,
Is this a duplicate patch?
There was a patch you sent: [edk2-devel] [PATCH 1/1] AMD/AmdMinBoardPkg:
Implements PCI hotplug init protocol, they both create PciHotPlug.c and
PciHotPlug.inf.
Thanks
Abner
> -Original Message-
> From: Abdul Latee
[AMD Official Use Only - General]
Hi Abdul,
Is this change just a initial patch that clone PciHotPlugInit.c to under
AmdMIniBordPkg? Do we have AMD modification on this file? Because I don't see
AMD license in the file header.
Just curious about why do we change the GUID of DSC file?
Thanks
Abn
From: Gua Guo
Ideally behavior is like below order that can support one local build
machine, clone multiple Edk2, some of edk2 repo use old tag and
some of edk2 repo use new tag, they can both support on one machine.
1. if defined PYTHON_COMMAND only
- use PYTHON_COMMAND = user assigned
2. if
On Thu, 25 May 2023 at 19:21, Oliver Smith-Denny
wrote:
>
> On 5/25/2023 7:30 AM, Ard Biesheuvel wrote:
> > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4468
> >
> >
> >
> > This is a proof-of-concept RFC that implements a PEI phase PPI to manage
> >
> > memory permission attributes, and wi
On Thu, 25 May 2023 at 19:21, Oliver Smith-Denny
wrote:
>
> On 5/25/2023 7:30 AM, Ard Biesheuvel wrote:
> > Add a notification callback to the PEI core to grab a reference to the
> > memory attributes PPI as soon as it is registered, and use it in the
> > image loader to set restricted memory perm
Pedro and Oliver,
Yes. Renaming the struct members is my preferred solution.
This is why I did not send this as a code review as an
official change request.
It was just to complete the set of options to consider
* No code changes. Figure out compiler flags to address.
STATUS: No complete so
On Thu, May 25, 2023 at 6:43 PM Oliver Smith-Denny
wrote:
>
> Hi Mike,
>
> Thanks for looking for solutions here. This one feels like
> quite a back bend, I'm imagining reading code and coming
> across TpmStruct.CPLUSPLUS_OPERATOR_KEYWORD and having to
> dig around quite a lot to see what goodness
Hi Mike,
Thanks for looking for solutions here. This one feels like
quite a back bend, I'm imagining reading code and coming
across TpmStruct.CPLUSPLUS_OPERATOR_KEYWORD and having to
dig around quite a lot to see what goodness is going
on. Because we would have to update the C files, too, right,
On 5/25/2023 7:30 AM, Ard Biesheuvel wrote:
Add a notification callback to the PEI core to grab a reference to the
memory attributes PPI as soon as it is registered, and use it in the
image loader to set restricted memory permissions after loading the
image if the image was loaded into memory.
T
On 5/25/2023 7:30 AM, Ard Biesheuvel wrote:
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4468
This is a proof-of-concept RFC that implements a PEI phase PPI to manage
memory permission attributes, and wires it up to the PEI image loader so
that shadowed PEIMs as well as the DXE core a
Hi Pedro,
Thanks for the feedback!
Applying your pattern to edk2, we find all the usage of c++
reserved keywords and replace with a macro. We then define
that macro to either be the actual c++ reserved keyword if
build with a C compiler and rename the keyword if building
with a c++ compiler. Th
On Thu, 25 May 2023 at 18:49, Pete Batard wrote:
>
> The newly released TF-A v2.9 contains a fix for an issue that has been
> affecting some Raspberry Pi 3 users, when trying to issue a reboot with
> some types of SD cards (See: pftf/RPi3#17, pftf/RPi3#24).
>
> This fix is documented at:
> https:/
The newly released TF-A v2.9 contains a fix for an issue that has been
affecting some Raspberry Pi 3 users, when trying to issue a reboot with
some types of SD cards (See: pftf/RPi3#17, pftf/RPi3#24).
This fix is documented at:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/20297
On Tue, 2 May 2023 at 07:59, Gerd Hoffmann wrote:
>
> Check whenever flash is actually writable.
>
This is a bit too terse. Could you explain why this is needed, and why
this approach is suitable?
> Signed-off-by: Gerd Hoffmann
> ---
> OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlash.c | 14 ++
On Fri, 19 May 2023 at 16:56, Sami Mujawar wrote:
>
> Kvmtool allows guest VMs to be launched with or without
> a CFI flash device. The guest hardware configuration can
> be seen in the device tree that Kvmtool hands off to the
> guest firmware.
>
> Therefore, add support to dynamically detect if
On Wed, 17 May 2023 at 12:24, Gerd Hoffmann wrote:
>
>
>
> Gerd Hoffmann (3):
> OvmfPkg/PlatformInitLib: check PcdUse1GPageTable
> OvmfPkg/OvmfPkgIa32X64: enable 1G pages
> OvmfPkg/MicrovmX64: enable 1G pages
>
Acked-by: Ard Biesheuvel
> OvmfPkg/Microvm/MicrovmX64.dsc
On Tue, 16 May 2023 at 11:48, Gerd Hoffmann wrote:
>
> Flip the default for IO address space reservations for PCI(e) bridges
> and root ports with hotplug support from TRUE to FALSE.
>
> PCI(e) bridges will still get IO address space assigned in case:
>
> (a) Downstream devices actually need IO
On Thu, May 25, 2023 at 7:27 AM Ard Biesheuvel wrote:
> On Wed, 24 May 2023 at 20:13, Tuan Phan wrote:
> >
> >
> >
> > On Mon, Mar 6, 2023 at 9:53 AM Ard Biesheuvel wrote:
> >>
> >> On Mon, 6 Mar 2023 at 18:33, Tuan Phan wrote:
> >> >
> >> > The flash base address can be added to GCD before th
If the associated PCD is set to TRUE, use the memory attribute PPI to
remap the stack non-executable. This provides a generic method for doing
so, which will be used by ARM and AArch64 as well once they move to the
generic DxeIpl handoff implementation.
Signed-off-by: Ard Biesheuvel
---
MdeModul
Now that we have a generic method to manage memory permissions using a
PPI, we can switch to the generic version of the DXE handoff code in
DxeIpl, and drop the ARM specific version.
Signed-off-by: Ard Biesheuvel
---
MdeModulePkg/Core/DxeIplPeim/Arm/DxeLoadFunc.c | 71
MdeMo
The Risc-V and LoongArch specific versions of the DXE core handoff code
in DxeIpl are essentially copies of the EBC version (modulo the
copyright in the header and some debug prints in the code).
In preparation for introducing a generic PPI based method to implement
the non-executable stack, let's
Add a notification callback to the PEI core to grab a reference to the
memory attributes PPI as soon as it is registered, and use it in the
image loader to set restricted memory permissions after loading the
image if the image was loaded into memory.
There are two use cases for this:
- when the DX
Implement the newly defined PPI that permits the PEI core and DXE IPL to
manage memory permissions on ranges of DRAM, for doing things like
mapping the stack non-executable, or granting executable permissions to
shadowed PEIMs.
Signed-off-by: Ard Biesheuvel
---
ArmPkg/Drivers/CpuPei/CpuPei.c |
Define a PPI interface that may be used by the PEI core or other PEIMs
to manage permissions on memory ranges. This is primarily intended for
restricting permissions to what is actually needed for correct execution
by the code in question, and for limiting the use of memory mappings
that are both w
The RISC-V version of the DXE IPL does not implement setting the stack
NX, so before switching to an implementation that will ASSERT() on the
missing support, drop the PCD setting that enables it.
Signed-off-by: Ard Biesheuvel
---
OvmfPkg/RiscVVirt/RiscVVirtQemu.dsc | 6 --
1 file changed, 6
Currently, ARM's CPU PEIM depexes on PEI permanent memory being
installed, but functionally, it does not actually depend on that at all.
So let's drop the DEPEX.
Signed-off-by: Ard Biesheuvel
---
ArmPkg/Drivers/CpuPei/CpuPei.inf | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git
Now that ArmSetMemoryAttributes() permits a mask to be provided, we can
simplify the implementation the UEFI memory attribute protocol
substantially, and just pass on the requested mask to be set or cleared
directly.
Signed-off-by: Ard Biesheuvel
---
ArmPkg/Drivers/CpuDxe/MemoryAttribute.c | 50
Currently, ArmSetMemoryAttributes () takes a combination of
EFI_MEMORY_xx constants describing the memory type and permission
attributes that should be set on a region of memory. In cases where the
memory type is omitted, we assume that the memory permissions being set
are final, and that existing
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4468
This is a proof-of-concept RFC that implements a PEI phase PPI to manage
memory permission attributes, and wires it up to the PEI image loader so
that shadowed PEIMs as well as the DXE core are remapped with the
appropriate, restricted memor
On Wed, 24 May 2023 at 20:13, Tuan Phan wrote:
>
>
>
> On Mon, Mar 6, 2023 at 9:53 AM Ard Biesheuvel wrote:
>>
>> On Mon, 6 Mar 2023 at 18:33, Tuan Phan wrote:
>> >
>> > The flash base address can be added to GCD before this driver run.
>> > So only add it if it has not been done.
>> >
>>
>> How
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