From: Yong Li
Impelement the SpeculationBarrier with implementations consisting of
fence instruction which provides finer-grain memory orderings.
Data Barrier: fence rw,rw
Instruction Barrier: fence.i; fence r,r
More detail is in Chapter 17, RVWMO Memory Consistency Model
https://github.com/riscv
The timer compare register is 64-bit so simplifying the delay
function.
Signed-off-by: Tuan Phan
---
MdePkg/Include/Register/RiscV64/RiscVImpl.h | 1 -
.../BaseRiscV64CpuTimerLib/CpuTimerLib.c | 62 +--
2 files changed, 28 insertions(+), 35 deletions(-)
diff --git a/MdeP
SbiSetTimer expects core tick value.
Signed-off-by: Tuan Phan
---
.../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf | 3 +++
UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 26 ---
UefiCpuPkg/CpuTimerDxeRiscV64/Timer.h | 2 +-
3 files changed, 26 insertions(+), 5 deletions(
Normally, DXE driver would add device resource to GCD before start using.
But some key resources such as uart, flash base address are being accessing
directly in some core modules.
Those resources should be populated to HOB in SEC phase so they are
added to GCD before anyone can access them.
Sign
Move initialization of local variable structure from declaration
to statements to fix VS2015x86 build break.
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: Jordan Justen
Cc: Gerd Hoffmann
Signed-off-by: Michael D Kinney
---
OvmfPkg/VirtioSerialDxe/VirtioSerial.c | 10 +-
1 file changed, 5 ins
The flash base address can be added to GCD before this driver run.
So only add it if it has not been done.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +++
1 file changed, 16 insertions(+), 9 deletions(-)
diff --
The size should be for single region, not the whole firmware FD.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
.../Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c| 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
a/OvmfPkg/RiscVVirt/Library/VirtNorFlas
During CpuDxe initialization, MMU will be setup with the highest
mode that HW supports.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +-
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 +
UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV6
MMU now is initialized in CpuDxe. There is no point to set satp to bare
mode as that should be the default mode when booting edk2.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
OvmfPkg/RiscVVirt/Sec/Memory.c | 18 ++
The satp mode bits shift is used cross modules. It should be defined
in one place.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/MdePkg/Include/Register/RiscV6
Add an API to retrieve satp register value.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
MdePkg/Include/Library/BaseLib.h | 5 +
MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8
2 files changed, 13 insertions(+)
diff --git a/MdePkg/Include/Library/BaseLib.h b/
RISC-V: Add MMU support
This series adds MMU support for RISC-V. Only SV39/48/57 modes
are supported and tested. The MMU is required to support setting
page attribute which is the first basic step to support security
booting on RISC-V.
There are three parts:
1. Add MMU base library. MMU will be e
That looks good. Thanks!
--
Rebecca Cran
On 5/26/23 10:56 AM, Guo, Gua wrote:
@Rebecca Cran
I update v2 patch on the PR https://github.com/tianocore/edk2/pull/4431
Could you help to check about whether meet your expectation ?
Thanks,
Gua
-Original Message-
From: Rebecca Cran
Sen
@Rebecca Cran
I update v2 patch on the PR https://github.com/tianocore/edk2/pull/4431
Could you help to check about whether meet your expectation ?
Thanks,
Gua
-Original Message-
From: Rebecca Cran
Sent: Saturday, May 27, 2023 12:30 AM
To: Guo, Gua ; devel@edk2.groups.io
Cc: Gao, Limi
On 5/25/23 6:09 PM, gua@intel.com wrote:
-%PYTHON_COMMAND% %BASE_TOOLS_PATH%\Tests\PythonTest.py %PYTHON_VER_MAJOR% %PYTHON_VER_MINOR% >NUL 2>NUL
-if %ERRORLEVEL% EQU 1 (
- echo.
- echo !!! ERROR !!! Python %PYTHON_VER_MAJOR%.%PYTHON_VER_MINOR% or newer is
required.
- echo.
- goto en
Following procedures are perf-logged:
* SmmReadyToBootHandler
* SmmReadyToLockHandler
* SmmEndOfDxeHandler
* SmmEntryPoint
(It's the main routine run in BSP when SMI happens.)
* SmiManage
Cc: Jian J Wang
Cc: Liming Gao
Cc: Jiaxin Wu
---
MdeModulePkg/Core/PiSmmCore/PiSmmCore.c | 14 ++
The patch adds perf-logging for the following potential
time-consuming BSP procedures:
* PiCpuSmmEntry
- SmmRelocateBases
* ExecuteFirstSmiInit
* BSPHandler
- SmmWaitForApArrival
- PerformRemainingTasks
* InitPaging
* SetMemMapAttributes
* SetUefiMemMapAttributes
* SetPag
Ray Ni (3):
UefiCpuPkg/CpuSmm: Add perf-logging for time-consuming BSP procedures
UefiCpuPkg/CpuSmm: Add perf-logging for MP procedures
MdeModulePkg/SmmCore: Add perf-logging for time-consuming procedures
MdeModulePkg/Core/PiSmmCore/PiSmmCore.c | 14 ++-
MdeModulePkg/Core/PiSmmCore/
MP procedures are those procedures that run in every CPU thread.
The EDKII perf infra is not MP safe so it doesn't support to be called
from those MP procedures.
The patch adds SMM MP perf-logging support in SmmMpPerf.c.
The following procedures are perf-logged:
* SmmInitHandler
* SmmCpuFeaturesRe
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