Hey Yi,
I agree with the flow you have in the PR link and removing the extra protocol
locate.
My only comment is to align your comments with the commenting style of the file.
Instead of /**/, use // for both single and multi-line comments.
Example included in the comments on the PR.
Thanks,
Zac
On Thu, Jun 22, 2023 at 11:41 AM Tuan Phan wrote:
>
>
> On Tue, May 30, 2023 at 10:38 AM Tuan Phan via groups.io ventanamicro@groups.io> wrote:
>
>>
>>
>> On Mon, May 29, 2023 at 7:07 AM Ard Biesheuvel wrote:
>>
>>> On Sat, 27 May 2023 at 01:18, Tuan Phan wrote:
>>> >
>>> > Normally, DXE d
Hi Kun,
Thank you for this patch.
Please find my response inline marked [SAMI].
Regards,
Sami Mujawar
On 08/06/2023 09:44 pm, Kun Qin wrote:
From: Kun Qin
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=4464
This change introduced the MM communicate support in PEI phase for ARM
based pl
On Tue, May 30, 2023 at 10:38 AM Tuan Phan via groups.io wrote:
>
>
> On Mon, May 29, 2023 at 7:07 AM Ard Biesheuvel wrote:
>
>> On Sat, 27 May 2023 at 01:18, Tuan Phan wrote:
>> >
>> > Normally, DXE driver would add device resource to GCD before start
>> using.
>> > But some key resources such
Thanks a lot, Sami!
On 6/22/2023 12:06 AM, Sami Mujawar wrote:
Hi Kun,
Apologies for the delay in reviewing.
I will take a look at this series shortly and get back.
Regards,
Sami Mujawar
On 22/06/2023, 06:07, "Kun Qin" mailto:kuqi...@gmail.com>>
wrote:
Hi Arm and MdeModule package mainta
Hi Pedro,
Thanks for your feedback.
The sample code what I listed in last mail is from/owned by another team, and I
didn't find other special #ifndef case for RSIC-V building so far.
RISC-V is an new processor architecture in edk2 implementation, in our internal
BIOS code, there are many simila
Also, a gentle ping on this topic. Could any maintainer help reviewing
this change?
Any feedback is appreciated.
Regards,
Kun
On 6/6/2023 6:07 PM, Kun Qin via groups.io wrote:
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4467
This is a follow-up of a previously submitted patch series
On Thu, Jun 22, 2023 at 10:59 AM Xue, Gavin wrote:
>
> Hi Pedro,
>
> Thanks for your feedback.
>
> The sample code what I listed in last mail is from/owned by another team, and
> I didn't find other special #ifndef case for RSIC-V building so far.
> RISC-V is an new processor architecture in edk2
Reviewed-by: Eric Dong
-Original Message-
From: Ni, Ray
Sent: Wednesday, June 21, 2023 2:01 PM
To: Liu, Zhiguang ; Dong, Eric
Cc: devel@edk2.groups.io; Ni, Ray
Subject: RE: [edk2-devel] [PATCH v2 0/3] UefiCpuPkg/ResetVector: Remove
pre-built binaries
I updated the patch per Zhiguang
Use the latest Linux container image (from 2023-05-30).
It uses Qemu 8.0.0 and gcc 12.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4324
Signed-off-by: Oliver Steffen
Acked-by: Ard Biesheuvel
Reviewed-by: Michael Kubacki
---
.azurepipelines/templates/defaults.yml | 2 +-
1 file changed
Use the latest Linux container image (from 2023-05-30).
It uses Qemu 8.0.0 and gcc 12.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4324
PR: https://github.com/tianocore/edk2/pull/4460
v2:
- Collect RBs and Acks
- Rerun CI with current master branch
v1:
- intial version
Oliver Steffen (1
Check we have any data left (Len > 0) before advancing the Data pointer
and reducing Len. Avoids wrapping Len.
Also replace the AsciiStrLen() call with an open-coded loop which
likewise checks Len to make sure we don't overrun the buffer.
Bugzilla: https://bugzilla.tianocore.org/show_bug.cgi?id=
Thank you very much to contribute this patch. Here is my feedback.
1) I don't believe that you cannot use digest size to determine the algorithm,
because different hash algorithm may have same time. E.g. SHA256 and SHA3_256.
+ if (DigestSize == SHA256_DIGEST_SIZE) {
+Status = CalculatePrivA
Hi Kun,
Apologies for the delay in reviewing.
I will take a look at this series shortly and get back.
Regards,
Sami Mujawar
On 22/06/2023, 06:07, "Kun Qin" mailto:kuqi...@gmail.com>>
wrote:
Hi Arm and MdeModule package maintainers,
This patch series has been sent out for almost 2 weeks wi
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