Reviewed-by: Sunil V L
On Fri, Jun 23, 2023 at 11:39:27AM -0700, Tuan Phan wrote:
> This series adds MMU support for RISC-V. Only SV39/48/57 modes
> are supported and tested. The MMU is required to support setting
> page attribute which is the first basic step to support security
> booting on RIS
On Fri, 14 Jul 2023 at 22:28, Tom Lendacky wrote:
>
> Commit 63c50d3ff2854a76432b752af4f2a76f33ff1974 changed the check that is
> used to determine if SEV-ES is active. Originally, a CMP instruction with
> a supporting JZ instruction was used for the check. It was changed to use
> the BT instructi
Commit 63c50d3ff2854a76432b752af4f2a76f33ff1974 changed the check that is
used to determine if SEV-ES is active. Originally, a CMP instruction with
a supporting JZ instruction was used for the check. It was changed to use
the BT instruction but not JZ instruction. The result of a BT instruction
cha
On Fri, Jul 14, 2023 at 3:24 AM Sunil V L wrote:
> On Fri, Jun 23, 2023 at 11:39:34AM -0700, Tuan Phan wrote:
> > During CpuDxe initialization, MMU will be setup with the highest
> > mode that HW supports.
> >
> > Reviewed-by: Andrei Warkentin
> > Signed-off-by: Tuan Phan
> > ---
> Hi Tuan,
>
>
During CpuDxe initialization, MMU will be setup with the highest
mode that HW supports.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
---
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +-
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h
There is no point to set satp to bare mode as that should be the
default mode when booting edk2.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
Reviewed-by: Sunil V L
---
OvmfPkg/RiscVVirt/Sec/Memory.c | 18 ++
1 file changed, 2 insertions(+), 16 deletions(-)
diff --gi
Make sure VirtNorFlashDxe loaded before VariableRuntimeDxe as it
is the backend flash driver.
Signed-off-by: Tuan Phan
---
OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 10 ++
1 file changed, 10 insertions(+)
diff --git a/OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf
b/OvmfPkg/RiscVVirt/RiscVVirtQemu.fd
Normally, DXE driver would add device resource to GCD before start using.
But some key resources such as uart used for printing info at very early
stage.
Those resources should be populated to HOB in SEC phase so they are
added to GCD before MMU enabled.
Signed-off-by: Tuan Phan
Reviewed-by: And
The size should be for single region, not the whole firmware FD.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
Reviewed-by: Sunil V L
---
.../Library/VirtNorFlashPlatformLib/VirtNorFlashStaticLib.c| 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
a/OvmfPkg/RiscV
The satp mode bits shift is used cross modules. It should be defined
in one place.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
Reviewed-by: Sunil V L
Reviewed-by: Michael D Kinney
---
MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 ---
1 file changed, 4 insertions(+), 3 de
Add an API to retrieve satp register value.
Signed-off-by: Tuan Phan
Reviewed-by: Andrei Warkentin
Reviewed-by: Sunil V L
---
MdePkg/Include/Library/BaseLib.h | 5 +
MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8
2 files changed, 13 insertions(+)
diff --git a/MdePkg/Incl
This series adds MMU support for RISC-V. Only SV39/48/57 modes
are supported and tested. The MMU is required to support setting
page attribute which is the first basic step to support security
booting on RISC-V.
There are two parts:
1. Add MMU base library. MMU will be enabled during
CpuDxe initia
Onemore need change beside fixs:16acacf24c ("OvmfPkg: fix PlatformConfig")
Find by sct case:ExtractConfigConformance fail.
Signed-off-by: Yin Wang
---
OvmfPkg/PlatformDxe/Platform.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/OvmfPkg/PlatformDxe/Platform.c b/OvmfPkg/Platf
>
> To please both sides, how about:
> 1. Remove the 'Status' assignment of the return value from
> SetDriveParameters()
> Based on my findings (https://edk2.groups.io/g/devel/message/106844), the
> successful execution of SetDriveParameters() is not mandatory for
> initializing
> IDE mode hard dis
[AMD Official Use Only - General]
Reviewed-by: Abner Chang
> -Original Message-
> From: Nickle Wang
> Sent: Thursday, July 13, 2023 5:25 PM
> To: devel@edk2.groups.io
> Cc: Chang, Abner ; Igor Kulchytskyy
> ; Nick Ramirez
> Subject: [PATCH] RedfishPkg/RedfishRestExDxe: reset session wh
Update the TF-A binaries to have Neoverse-V1 cpu support.
This support was merged into TF-A:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/21813
This allows SBSA Reference Platform to boot Linux on "neoverse-v1" cpu.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/Sbsa/Re
On Fri, Jun 23, 2023 at 11:39:34AM -0700, Tuan Phan wrote:
> During CpuDxe initialization, MMU will be setup with the highest
> mode that HW supports.
>
> Reviewed-by: Andrei Warkentin
> Signed-off-by: Tuan Phan
> ---
Hi Tuan,
CI tests are failing for these changes primarily due to code formatt
Hi, Pedro
> Nit: AcpiView, not Acpivew
> Nit: information
> typo: trigger mode
Thanks to find out type :)
>>
>> + UINT8 TriggerMode;
>>
>> +
>>
>> + TriggerMode = (*(UINT8 *)Ptr);
> You don't need parenthesis here, nor a cast.
Yes Thanks..!
>
>>
>> +
>>
>> + Print (
>>
>> +L"%s(%d)",
>
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