Modify the gSmmBaseHobGuid consumption code to
remove the asuumption that there is only one
gSmmBaseHobGuid. If the CPU number is big enough,
there will be more than one SmmBaseHob in the
HOB list.
Signed-off-by: Dun Tan
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
---
UefiCpuP
Cache core type in MpInfo2 HOB by CpuMpPei module.
Signed-off-by: Dun Tan
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
---
UefiCpuPkg/CpuMpPei/CpuMpPei.c | 59
+--
UefiCpuPkg/CpuMpPei/CpuMpPei.h | 2 ++
2 files changed,
Add new field CoreType in gMpInformationHobGuid2
Signed-off-by: Dun Tan
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
---
UefiCpuPkg/Include/Guid/MpInformation2.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/UefiCpuPkg/Include/Guid/MpInformation2.h
b/UefiCpuPkg/Include
Consume MpInfo2Hob in PiSmmCpuDxe driver to get
NumberOfProcessors, MaxNumberOfCpus and
EFI_PROCESSOR_INFORMATION for all CPU from the
MpInformation2 HOB.
This can avoid calling MP service.
Signed-off-by: Dun Tan
Cc: Eric Dong
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Gerd Hoffmann
---
UefiCpuPkg/PiSmm
Build MpInfo2HOB in CpuMpPei module so that later
PiSmmCpuDxe or other StandaloneMm module can consume
the HOB.
Since there might be more one gMpInformationHobGuid2
in HOB list, CpuMpPei create a gMpInformationHobGuid2
with 0 value NumberOfProcessors field in the end of the
process to indicate it's
Create gMpInformationHobGuid2 in UefiCpuPkg.
Currently, there is a gMpInformationHobGuid defined,
created and consumed only in StandaloneMmPkg. The HOB
contains the EFI_PROCESSOR_INFORMATION structure for
each CPU and the number of processors. This is the same
as the information that PiSmmCpuDxeSm
Create and consume gMpInformationHobGuid2 in UefiCpuPkg in this patch series.
Currently, there is a gMpInformationHobGuid defined, created and consumed only
in StandaloneMmPkg.
The HOB contains the EFI_PROCESSOR_INFORMATION structure for each CPU and the
number of processors.
This is the same as
Patch pushed:
https://github.com/tianocore/edk2-platforms/commit/f446fff05003f69a4396b2ec375301ecb5f63a2a
Thanks,
Chasel
> -Original Message-
> From: Chiang, Chris
> Sent: Monday, December 4, 2023 12:51 AM
> To: devel@edk2.groups.io
> Cc: Chiang, Chris ; Chiu, Chasel
> ; Desimone, Na
*Reminder: TianoCore Bug Triage - APAC / NAMO*
*When:*
Tuesday, December 5, 2023
6:30pm to 7:30pm
(UTC-08:00) America/Los Angeles
*Where:*
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[AMD Official Use Only - General]
That's fine Mike, I will just create a PR and update it with your Acked-by.
Abner
> -Original Message-
> From: Mike Maslenkin
> Sent: Monday, December 4, 2023 6:59 PM
> To: devel@edk2.groups.io; Chang, Abner
> Cc: Nickle Wang ; Igor Kulchytskyy
> Subj
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Hello:
I have a question which might not be applicable to the stock Tianocore
codebase, but I'm hoping maybe someone here might recognize what I'm asking
about and could give me some pointers.
I have A Board (tm) with Intel Raptor Lake CPU and a UEFI 2.7-based firmware
implementation on it. Ou
From: Chiang-Chris
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4612
Remove PeiDxeTpmPlatformHierarchyLib in Tcg/Library
Signed-off-by: Chiang-Chris
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Liming Gao
Cc: Eric Dong
---
Platform/Intel/MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc
Reviewed-by: Rodrigo Gonzalez del Cueto
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U
*Tools, CI, Code base construction meeting series*
*When:*
Monday, December 4, 2023
4:30pm to 5:30pm
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*Where:*
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Monday, December 4, 2023
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*Where:*
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> -Original Message-
> From: Pedro Falcato
> Sent: Monday, December 4, 2023 11:59 AM
> To: devel@edk2.groups.io; Desimone, Nathaniel L
>
> Cc: Ni, Ray ; Kinney, Michael D
>
> Subject: Re: [edk2-devel] [PATCH v2] PcAtChipsetPkg: Fix AcpiTimerLib
> incompatibility with XhciDxe
>
On Mon, Dec 4, 2023 at 6:48 PM Nate DeSimone
wrote:
>
> The DXE & MM standalone variant of AcpiTimerLib defines a global
> named mPerformanceCounterFrequency. A global with an identical
> name is also present in MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
>
> Since XhciDxe has a dependency on TimerLib, th
The DXE & MM standalone variant of AcpiTimerLib defines a global
named mPerformanceCounterFrequency. A global with an identical
name is also present in MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
Since XhciDxe has a dependency on TimerLib, this can cause link
errors due to the same symbol being defined tw
The DXE & MM standalone variant of AcpiTimerLib defines a global
named mPerformanceCounterFrequency. A global with an identical
name is also present in MdeModulePkg/Bus/Pci/XhciDxe/Xhci.c
Since XhciDxe has a dependency on TimerLib, this can cause link
errors due to the same symbol being defined tw
Reviewed-by: Chasel Chiu
Thanks,
Chasel
> -Original Message-
> From: Chiang, Chris
> Sent: Monday, December 4, 2023 12:51 AM
> To: devel@edk2.groups.io
> Cc: Chiang, Chris ; Chiu, Chasel
> ; Desimone, Nathaniel L
> ; Gao, Liming ;
> Dong, Eric
> Subject: [PATCH v1] MinPlatformPkg:
Reviewed-by: Igor Kulchytskyy
Regards,
Igor
-Original Message-
From: Nickle Wang
Sent: Monday, December 4, 2023 4:41 AM
To: devel@edk2.groups.io
Cc: Abner Chang ; Igor Kulchytskyy ; Nick
Ramirez
Subject: [EXTERNAL] [edk2-redfish-client][PATCH v2]
RedfishClientPkg/RedfishFeatureUtility
On Mon, 4 Dec 2023 at 15:52, Gerd Hoffmann wrote:
>
> Hi,
>
> > > > That way you at least you know who you trust. Just remove shim. Have a
> > > > look
> > > > at how Amazon Linux 2023 did it [2] :))
>
> > > You are in the luxurious position to run your own distro on your own
> > > platform, wh
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Hi,
> > > That way you at least you know who you trust. Just remove shim. Have a
> > > look
> > > at how Amazon Linux 2023 did it [2] :))
> > You are in the luxurious position to run your own distro on your own
> > platform, which makes this totally easy.
> Sure, we're cheating a bit on x86.
Merged as b95395ba400e..3220cb309390
Thanks.
Regards,
Sami Mujawar
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Hi Levi,
Thank you for this patch.
Reviewed-by: Sami Mujawar
Regards,
Sami Mujawar
On 30/11/2023, 14:29, "levi.yun" mailto:yeoreum@arm.com>> wrote:
The edk2 commit 7284c44951cffd52f1a08367d91b5c63c7bb9c16
introduces a new library ImagePropertiesRecordLib to
consolidate the logic for
Tested for N1SDP.
Tested-by: Himanshu Sharma
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On Mon, 4 Dec 2023 at 13:38, Alexander Graf wrote:
>
>
> On 04.12.23 13:20, Gerd Hoffmann wrote:
> >Hi,
> >
> >> (hint: You really don't want or need shim on ARM. The only reason for shim
> >> is that on most x86 desktop systems, users will have the MS keys
> >> preinstalled. The MS Secure Boo
Hi,
> (hint: You really don't want or need shim on ARM. The only reason for shim
> is that on most x86 desktop systems, users will have the MS keys
> preinstalled. The MS Secure Boot concept however is terribly broken: Any
> compromise of any of the MS signed binaries jeopardizes your boot chain
Fan:
I add my comment below.
> -邮件原件-
> 发件人: devel@edk2.groups.io 代表 Wang Fan
> 发送时间: 2023年12月4日 18:31
> 收件人: Ni, Ray ; devel@edk2.groups.io; Gao, Liming
> ; Kinney, Michael D
>
> 抄送: Jiang, Guomin
> 主题: Re: [edk2-devel] [PATCH V2 1/1] MdeModulePkg: Support customized
> FV Migration
On Mon, Dec 04, 2023 at 11:57:43AM +0100, Ard Biesheuvel wrote:
> On Mon, Dec 4, 2023 at 11:53 AM Gerd Hoffmann wrote:
> >
> > > So let's introduce a QEMU command line option to indicate that the
> > > protocol should not be exposed at all.
> > >
> > > -fw_cfg opt/org.tianocore/DisableMemAttrPro
Hi Abner,
You can add my Acked-by to each commit, if it won't take to much time
for resending series, etc.
Regards,
Mike
On Mon, Dec 4, 2023 at 12:08 PM Chang, Abner via groups.io
wrote:
>
> [AMD Official Use Only - General]
>
> Hi Mike, would you like to having you Acked-by on each commit?
>
On Mon, Dec 4, 2023 at 11:53 AM Gerd Hoffmann wrote:
>
> > So let's introduce a QEMU command line option to indicate that the
> > protocol should not be exposed at all.
> >
> > -fw_cfg opt/org.tianocore/DisableMemAttrProtocol,string=y
>
> Can we name this 'MemAttrProtocol={y,n}' so it works both
On Mon, Dec 4, 2023 at 11:45 AM Alexander Graf wrote:
>
>
> On 04.12.23 10:52, Ard Biesheuvel wrote:
> > From: Ard Biesheuvel
> >
> > Shim's PE loader uses the EFI memory attributes protocol in a way that
> > results in an immediate crash when invoking the loaded image unless the
> > base and siz
> So let's introduce a QEMU command line option to indicate that the
> protocol should not be exposed at all.
>
> -fw_cfg opt/org.tianocore/DisableMemAttrProtocol,string=y
Can we name this 'MemAttrProtocol={y,n}' so it works both ways (enabling
and disabling) without double negative?
The fedor
Hello everyone,
I am building the wilsonCity Rvp From the whitleyLake package inside
edk2-platforms. unfortunately i wasn't able to get the debug running
even though I tried everything but that isn't my problem right now
since I use POST codes on each part of code and check to see if the
codes are
Thank you Ray and Liming, for your comments.
Ray,
There's something to clarify on this HOB usage. In this patch, when this
Migration feature PCD is set to TRUE, the PeiCore will only migrate FVs which
are recorded by ToMigrateFvInfo hob (each FV should publish their own
ToMigrateFvInfo hob in
On Mon, 4 Dec 2023 at 10:52, Ard Biesheuvel wrote:
>
> From: Ard Biesheuvel
>
> Shim's PE loader uses the EFI memory attributes protocol in a way that
> results in an immediate crash when invoking the loaded image unless the
> base and size of its executable segment are both aligned to 4k.
>
> If
From: Ard Biesheuvel
Shim's PE loader uses the EFI memory attributes protocol in a way that
results in an immediate crash when invoking the loaded image unless the
base and size of its executable segment are both aligned to 4k.
If this is not the case, it will strip the executable permissions fr
Hi Igor,
Sorry for my delay response. Having three checks in
ValidateRedfishStringArrayValues is complicate to me so I took some time to
verify it on my system.
> Maybe their functionality can be combined in ValidateRedfishStringArrayValues?
> Some additional an out parameter from that function
Add function ValidateRedfishStringArrayValues to validate Redfish
request for string array type. There is case that user request
invalid string array and feature driver can not find corresponding
HII option.
Signed-off-by: Nickle Wang
Cc: Abner Chang
Cc: Igor Kulchytskyy
Cc: Nick Ramirez
---
[AMD Official Use Only - General]
Hi Mike, would you like to having you Acked-by on each commit?
Abner
> -Original Message-
> From: Mike Maslenkin
> Sent: Monday, December 4, 2023 3:18 PM
> To: Chang, Abner
> Cc: devel@edk2.groups.io; Nickle Wang ; Igor
> Kulchytskyy
> Subject: Re: [P
This PCD provides a way for platform to override any
HW features that are default enabled by previous stages
of FW (like OpenSBI). For the case where previous/prev
stage has disabled the feature, this override is not
useful and its usage should be avoided.
Cc: Ard Biesheuvel
Cc: Jiewen Yao
Cc: J
Use newly defined cache management operations for RISC-V where possible
It builds up on the support added for RISC-V cache management
instructions in BaseLib.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Laszlo Ersek
Signed-off-by: Dhaval Sharma
Acked-by: Laszlo Ersek
---
Notes:
Implement Cache Management Operations (CMO) defined by
RISC-V spec https://github.com/riscv/riscv-CMOs.
Notes:
1. CMO only supports block based Operations. Meaning cache
flush/invd/clean Operations are not available for the entire
range. In that case we fallback on fence.i instructions.
2. O
There are different ways to manage cache on RISC-V Processors.
One way is to use fence instruction. Another way is to use CPU
specific cache management operation instructions ratified as
per RISC-V ISA specifications to be introduced in future
patches. Current method is fence instruction based, ren
The declarations for cache Management functions belong to BaseLib
instead of instance source file. This helps with further restructuring
of cache management code for RISC-V.
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Laszlo Ersek
Signed-off-by: Dhaval Sharma
Reviewed-by: Laszlo
Implementing code to support Cache Management Operations (CMO) defined by
RISC-V CMO instructions.https://github.com/riscv/riscv-CMOs
This is a re-write of original series v5.
The patchset contains 5 patches- created based on V5 feedback.
1. Restructuring of existing code and move instruction decla
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