Subject: [PATCH] IntelSiliconPkg: Add IgdOpRegion32.h to support IGD OpRegion
v3.2
- Backlight related fields in MBOX2 has uncalibrated brightness support
- Valid Bit added for BCL in MBOX2
Signed-off-by: Ck, Chitralekha
Cc: Rangasai V Chaganty
Cc: Ashraf Ali S
Cc: Ray Ni
---
.../Include
: Rangasai V Chaganty
Cc: Ashraf Ali S
Co-authored-by: Ken Lautner
Signed-off-by: Michael Kubacki
---
Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdCoreDxe/BmDma.c |
4 ++--
Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdCoreDxe/VtdLog.c |
12 ++--
Silicon/Intel
/PatchFv.py: FIX for GCC 32BIT build error
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4762
Map file generating 8 byte address offset is not matched with the pattern
defined in patchFv tool resulting build error.
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Duggapu Chinni B
Cc: Ashraf Ali S
Cc: Ted
Cc: Ashraf Ali S
Cc: Susovan Mohapatra
Signed-off-by: Gua Guo
---
IntelFsp2Pkg/Tools/PatchFv.py | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py
index 73ab877c71..bd9aa71e3c 100644
--- a
Cc: Ashraf Ali S
Cc: Susovan Mohapatra
Signed-off-by: Gua Guo
---
IntelFsp2Pkg/Tools/GenCfgOpt.py | 96 -
1 file changed, 48 insertions(+), 48 deletions(-)
diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenCfgOpt.py
index 13be81ddbc
Hi @Liming Gao @Rebecca Cran
Is this patch already pushed? As its been already reviewed.
Thanks.,
S, Ashraf Ali
-Original Message-
From: devel@edk2.groups.io On Behalf Of Ashraf Ali S
Sent: Monday, March 11, 2024 5:01 PM
To: devel@edk2.groups.io; Chen, Christine
Cc: Rebecca Cran
GetFspPeiCoreImageBase
- PeiCore:BASE
PreFspSec:SecEntryRelativeOff PreFspSec:AsmGetFspOriginalEntry
- Fsp24SecCoreS:FspSiliconInitApi
Cc: Chasel Chiu mailto:chasel.c...@intel.com>>
Cc: Nate DeSimone
mailto:nathaniel.l.desim...@intel.com>>
Cc: D
hasel Chiu
Cc: Nate DeSimone
Cc: Duggapu Chinni B
Cc: Star Zeng
Cc: Ted Kuo
Cc: Ashraf Ali S
Cc: Susovan Mohapatra
Signed-off-by: Zhiguang Liu
---
IntelFsp2Pkg/Tools/PatchFv.py | 1 +
IntelFsp2Pkg/Tools/UserManuals/PatchFvUserManual.md | 3 ++-
2 files changed, 3
, Susovan
Subject: [PATCH] IntelFsp2Pkg/Tools: Updated iterator usage for Python 3
compatibility
Updated iterator usage for Python 3 compatibility
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Duggapu Chinni B
Cc: Star Zeng
Cc: Ted Kuo
Cc: Ashraf Ali S
Cc: Susovan Mohapatra
Signed-off-by: Zhiguang
) to
> cover both debug builds and release builds.
>
> Signed-off-by: Du Lin
> Cc: Ashraf Ali S
> Cc: Chasel Chiu
> Cc: Chen Gang C
> Cc: Duggapu Chinni B
> Cc: Nate DeSimone
> Cc: Star Zeng
> Cc: Susovan Mohapatra
> Cc: Ted Kuo
> ---
> IntelFsp2Wr
by enhancing the error handling of FspmWrapperInit() to cover
both debug builds and release builds.
Signed-off-by: Du Lin
Cc: Ashraf Ali S
Cc: Chasel Chiu
Cc: Chen Gang C
Cc: Duggapu Chinni B
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Susovan Mohapatra
Cc: Ted Kuo
---
.../FspmWrapperPeim
Cc: Ashraf Ali S
Cc: Chasel Chiu
Cc: Chen Gang C
Cc: Duggapu Chinni B
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Susovan Mohapatra
Cc: Ted Kuo
---
.../Library/BaseFspMeasurementLib/FspMeasurementLib.c | 4
1 file changed, 4 insertions(+)
diff --git
a/IntelFsp2WrapperP
Thanks for the review.
I have triggered the PR under basetools :
https://github.com/tianocore/edk2-basetools/pull/122
Thanks.,
S, Ashraf Ali
-Original Message-
From: devel@edk2.groups.io On Behalf Of Yuwei Chen
Sent: Monday, March 11, 2024 1:22 PM
To: S, Ashraf Ali ; devel@edk2.groups.
When the FMMTConf.ini file has empty lines then it used to throw errors
GuidTool load error!, this patch is to skip checking for empty lines in
the ini file
Cc: Rebecca Cran
Cc: Liming Gao
Cc: Bob Feng
Cc: Yuwei Chen
Cc: Chen Christine
Cc: Chaganty Rangasai V
Signed-off-by: Ashraf Ali
---
ic error in the cache management of a file like this, it will cause
unexpected behavior and developers will not trust incremental builds.
Mike
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Ashraf
> Ali S
> Sent: Tuesday, January 16, 2024 11:55 PM
> To
PcdRecordList.json.
and rest of the flow remains same.
if there is no change in VPD/PCD read the output.txt and return the data
Cc: Yuwei Chen
Cc: Rebecca Cran
Cc: Liming Gao
Cc: Bob Feng
Cc: Amy Chan
Cc: Sai Chaganty
Cc: Digant H Solanki
Signed-off-by: Ashraf Ali S
---
.../Source/Python
Gao
Cc: Bob Feng
Cc: Amy Chan
Cc: Sai Chaganty
Signed-off-by: Ashraf Ali S
---
BaseTools/Source/Python/AutoGen/PlatformAutoGen.py | 2 ++
1 file changed, 2 insertions(+)
diff --git a/BaseTools/Source/Python/AutoGen/PlatformAutoGen.py
b/BaseTools/Source/Python/AutoGen/PlatformAutoGen.py
index
below for FSP-T UPD revsions and X64 feature.
- PcdFspWrapperResetVectorInFsp
- PcdFspWrapperBfvforResetVectorInFsp
- PcdFsptUpdHeaderRevision
- PcdFsptArchUpdHeaderRevision
Cc: Sai Chaganty
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Eric Dong
Cc: Ashraf Ali S
Cc: Chinni B Duggapu
Cc: Liming
o
> increase the page table size based on the input. default will be 512GB
> build option PAGE_TABLE_1G_SIZE is used to increase the page table
> size
>
> Cc: Rahul Kumar
> Cc: Ray Ni
> Cc: Catharine West
> Cc: V Sangeetha
> Signed-off-by: Ashraf Ali S
e DeSimone
Cc: Duggapu Chinni B
Cc: Ray Han Lim Ng
Cc: Star Zeng
Cc: Ted Kuo
Reviewed-by: Ashraf Ali S
Cc: Susovan Mohapatra
---
.../Tools/UserManuals/PatchFvUserManual.md| 38 +--
1 file changed, 19 insertions(+), 19 deletions(-)
diff --git a/IntelFsp2Pkg/Tools/U
: Ashraf Ali S
---
UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt | 4 ++--
UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf | 2 ++
UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm | 13 +++--
3 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt
b
Ni
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Duggapu Chinni B
Cc: Ray Han Lim Ng
Cc: Star Zeng
Cc: Ted Kuo
Cc: Ashraf Ali S
Cc: Susovan Mohapatra
---
IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/FspMultiPhaseLib.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/Intel
uot;
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4595
Fix build error when remove "-Wno-sometimes-uninitialized" option, Add variable
"FspMultiPhaseApiOffset" initialization.
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Chasel Chiu
Cc: Chen Gang C
Cc: Duggapu Chinni B
Cc:
Reviewed-by: Ashraf Ali S
Thanks.,
S, Ashraf Ali
-Original Message-
From: Ni, Ray
Sent: Wednesday, November 1, 2023 3:00 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; Desimone, Nathaniel L
; Duggapu, Chinni B
; Ng, Ray Han Lim ; Zeng,
Star ; Kuo, Ted ; S, Ashraf Ali
; Mohapatra
serving the 32 bytes before calling C routine.
Signed-off-by: Ray Ni mailto:ray...@intel.com>>
Cc: Chasel Chiu mailto:chasel.c...@intel.com>>
M: Nate DeSimone
mailto:nathaniel.l.desim...@intel.com>>
M: Duggapu Chinni B
mailto:chinni.b.dugg...@intel.com>>
M: Ray Han Lim Ng
Reviewed-by: Ashraf Ali S
Thanks.,
S, Ashraf Ali
-Original Message-
From: Laszlo Ersek
Sent: Wednesday, October 25, 2023 2:06 PM
To: edk2-devel-groups-io
Cc: Abdul Lateef Attar ; Abner Chang
; S, Ashraf Ali ; Chiu, Chasel
; Dong, Eric ; Gao, Liming
; Desimone, Nathaniel L
SP-SMM module need get and set FspSmmInit upd data pointer functions
> to get and set upd settings.
>
> Signed-off-by: Hongbin1 Zhang
> Cc: Chasel Chiu
> Cc: Nate DeSimone
> Cc: Duggapu Chinni B
> Cc: Ray Han Lim Ng
> Cc: Star Zeng
> Cc: Ted Kuo
> Cc: Ashraf Ali
Ray Ni
> Cc: Zhichao Gao
> Cc: Ashraf Ali S
> Cc: Chinni B Duggapu
> Signed-off-by: chitralekha ck
> ---
> .../Library/BaseBmpSupportLib/BmpSupportLib.c | 58
> +++
> 1 file changed, 33 insertions(+), 25 deletions(-)
>
> diff --git a/MdeModulePkg/Lib
Reviewed-by: Ashraf Ali S
-Original Message-
From: devel@edk2.groups.io On Behalf Of Michael Kubacki
Sent: Friday, June 30, 2023 8:03 AM
To: devel@edk2.groups.io
Cc: Ni, Ray ; Chaganty, Rangasai V
; Oram, Isaac W ; S,
Ashraf Ali
Subject: [edk2-devel] [edk2-platforms][PATCH v1 1/1
HI All
I signed up to work as Reviewer for InteFsp2Pkg and IntelFsp2WrapperPkg
Maintainer file has been already updated :
https://github.com/tianocore/edk2/blob/master/Maintainers.txt
Need help to add me to the edk-ii-reviewers team.
Ashraf Ali S ashraf.al...@intel.com<mailto:ashraf
Reviewed-by: Ashraf Ali S
-Original Message-
From: Chang, Hunter
Sent: Tuesday, June 13, 2023 6:10 PM
To: devel@edk2.groups.io
Cc: Chang, Hunter ; Ni, Ray ;
Chaganty, Rangasai V ; Oram, Isaac W
; S, Ashraf Ali ; Chen, Tina
; Chen, Arthur G
Subject: [PATCH v1] IntelSiliconPkg: Add
Reviewed-by: Ashraf Ali S
-Original Message-
From: Aishwarya, KurugoduMelmatamX
Sent: Monday, June 12, 2023 10:54 AM
To: devel@edk2.groups.io
Cc: Aishwarya, KurugoduMelmatamX ; Chiu,
Chasel ; Desimone, Nathaniel L
; Duggapu, Chinni B
; Chen, Gang C ; Zeng, Star
; Kuo, Ted ; S
Reviewed-by: Ashraf Ali S
-Original Message-
From: Aishwarya, KurugoduMelmatamX
Sent: Friday, June 9, 2023 7:10 PM
To: devel@edk2.groups.io
Cc: Aishwarya, KurugoduMelmatamX ; Chiu,
Chasel ; Desimone, Nathaniel L
; Duggapu, Chinni B
; Chen, Gang C ; Zeng, Star
; Kuo, Ted ; S, Ashraf
Reviewed-by: S, Ashraf Ali
-Original Message-
From: devel@edk2.groups.io On Behalf Of Tan, Ming
Sent: Monday, May 22, 2023 11:43 AM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; Duggapu, Chinni B
Subject: [edk2-devel] [PATCH] IntelFsp2WrapperPkg: Fix ASSERT when FSP-S/M use
FFS3
REF: h
, Susovan
Subject: [PATCH] Maintainers.txt: Update for IntelFsp2Pkg and
IntelFsp2WrapperPkg.
Add more maintainers and reviewers for these 2 packages.
Cc: Nate DeSimone
Cc: Duggapu Chinni B
Cc: Ray Han Lim Ng
Cc: Chen Gang C
Cc: Star Zeng
Cc: Ted Kuo
Cc: Ashraf Ali S
Cc: Susovan Mohapatra
Yes, you are right. Tested on the H/W, It clears the upper 32bits. 😊
From: devel@edk2.groups.io On Behalf Of Marvin Häuser
Sent: Sunday, March 19, 2023 3:07 PM
To: S, Ashraf Ali
Cc: devel@edk2.groups.io; Chiu, Chasel ; Desimone,
Nathaniel L ; Zeng, Star
Subject: Re: [edk2-devel] [PATCH v2] Int
Hi.,
Nope, it will not clear the upper 32bit right.
From: Marvin Häuser
Sent: Sunday, March 19, 2023 3:38 AM
To: S, Ashraf Ali ; devel@edk2.groups.io
Subject: Re: [edk2-devel] [PATCH v2] IntelFsp2Pkg: Fix NASM X64 build warnings.
Hi Ashraf,
”mov eax, eax” does clear the high 32 Bits of rax.
Hi., Chasel
RAX holds the FsptImageBaseAddress, the AND operation is performed to clear the
upper 32bits of RAX registers.
Don't we have to clear the upper 32bit of RAX registers?
-Original Message-
From: devel@edk2.groups.io On Behalf Of Chiu, Chasel
Sent: Friday, March 17, 2023 10:51
Function defination should match with declaration.
[-Wlto-type-mismatch]
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Sai Chaganty
Cc: Star Zeng
Signed-off-by: Ashraf Ali S
---
IntelFsp2Pkg/Library/BaseFspPlatformLib/FspPlatformNotify.c | 1 +
1 file changed, 1 insertion(+)
diff --git a
rewriting both FV header and VariableStore
header when VariableStore corruption happened.
Platform has to set PcdFlashVariableStoreType to inform SpiFvbService which
VariableStoreType should be rewritten.
Cc: Ashraf Ali S
Cc: Isaac Oram
Cc: Rangasai V Chaganty
Cc: Ray Ni
Cc: Michael Kubacki
adding the support for rewriting both FV header and VariableStore
header when VariableStore corruption happened.
Platform has to set PcdFlashVariableStoreType to inform SpiFvbService which
VariableStoreType should be rewritten.
Cc: Ashraf Ali S
Cc: Isaac Oram
Cc: Rangasai V Chaganty
Cc: Ray Ni
Cc
: Rangasai V Chaganty
Cc: Isaac Oram
Cc: Ashraf Ali S
---
Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/FirmwareVersionInfo.h |
1 +
1 file changed, 1 insertion(+)
diff --git
a/Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/FirmwareVersionInfo.h
b/Silicon/Intel/IntelSiliconPkg
PCIE Base Address is 64bit PCD and the Mem Limit UINT64.
so typecasting to 32bit is not needed.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4068
Signed-off-by: Ashraf Ali S
Cc: Ray Ni
Cc: Rangasai V Chaganty
Cc: Isaac Oram
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Isaac Oram
Cc
Reviewed-by: S, Ashraf Ali
Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd.
-Original Message-
From: Kinney, Michael D
Sent: Wednesday, November 16, 2022 1:54 PM
To: devel@edk2.groups.io
Cc: Ni, Ray ; Chaganty, Rangasai V
; Oram, Isaac W ; S,
Ashraf Ali
Subject: [Patch
Reviewed-by: S, Ashraf Ali
Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd.
-Original Message-
From: Kinney, Michael D
Sent: Thursday, November 10, 2022 11:54 PM
To: devel@edk2.groups.io
Cc: Ni, Ray ; Chaganty, Rangasai V
; Oram, Isaac W ; S,
Ashraf Ali
Subject: [Patch edk2
Hi.,
Instead of Hardcoded FSP ImageBase as 0x1C in FspHelper.nasm, can we have
struct from there we can get it. So that in future if the Header is changing
assembly code will not get impacted.
Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd.
-Original Message-
From: Kuo, Ted
Reviewed-by: Ashraf Ali S
Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd.
-Original Message-
From: devel@edk2.groups.io On Behalf Of Michael Kubacki
Sent: Wednesday, October 5, 2022 8:53 PM
To: devel@edk2.groups.io
Cc: S, Ashraf Ali ; Oram, Isaac W
; Chaganty, Rangasai V ;
Ni
thunking the PCIE base address will cause the distruption in the
execution flow when the PCIE base address is 64bit bit.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4068
Signed-off-by: Ashraf Ali S
Cc: Ray Ni
Cc: Rangasai V Chaganty
Cc: Isaac Oram
Cc: Chasel Chiu
Cc: Nate DeSimone
Reviewed-by: Ashraf Ali S
Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd.
-Original Message-
From: Singh, DeepakX
Sent: Tuesday, August 23, 2022 3:42 PM
To: devel@edk2.groups.io
Cc: Singh, DeepakX ; Ni, Ray ;
Chaganty, Rangasai V ; Oram, Isaac W
; S, Ashraf Ali ; Pir, Ovais
Add Ashraf Ali S as IntelSiliconPkg reviewers
Signed-off-by: Ashraf Ali S
Cc: Ray Ni
Cc: Rangasai V Chaganty
Cc: Isaac Oram
---
Maintainers.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Maintainers.txt b/Maintainers.txt
index 5e403ce851..3fe5dc21a8 100644
--- a/Maintainers.txt
Add Ashraf Ali S as IntelSiliconPkg reviewers
Signed-off-by: Ashraf Ali S
Cc: Ray Ni
Cc: Rangasai V Chaganty
Cc: Isaac Oram
---
Maintainers.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Maintainers.txt b/Maintainers.txt
index 5e403ce851..e2ca67a0f2 100644
--- a/Maintainers.txt
Hi,
For the register offset doing the division operation of having a size UINTN in
below code,
I think we should use DivU64x32 function for Division operation right, correct
me if I'm wrong.
Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd.
-Original Message-
From: devel
V Chaganty
Cc: Digant H Solanki
Cc: Sangeetha V
Signed-off-by: Ashraf Ali S
---
.../BaseFspDebugLibSerialPort.inf | 8 ++-
.../{Ia32 => }/FspDebug.nasm | 50 +--
2 files changed, 28 insertions(+), 30 deletions(-)
rename IntelFsp2Pkg/Libr
it's a IA32 MAX_ADDRESS = 0x_
for X64MAX_ADDRESS = 0x___ULL
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Kuo Ted
Cc: Duggapu Chinni B
Cc: Rangasai V Chaganty
Cc: Digant H Solanki
Cc: Sangeetha V
Signed-off-by: Ashraf Ali S
---
IntelFsp2Pkg/FspSe
Hi., Michael
The issue was coming due to assign UINTN to UINT32 (warning C4244: '=':
conversion from 'UINTN' to 'UINT32', possible loss of data)
I will fix this in my code instead of changing in the EDK2.
Closing this bug, Thanks
Happy New Year 😊
Regards,
te the EFI_PEI_GRAPHICS_INFO_HOB based on UEFI Spec 2.0
Signed-off-by: Ashraf Ali S
Cc: Rangasai V Chaganty
Cc: Digant H Solanki
Cc: Sangeetha V
Cc: Ray Ni
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
---
MdePkg/Include/Guid/GraphicsInfoHob.h | 2 +-
1 file changed, 1 insertion
Solanki
Cc: Sangeetha V
Cc: Ray Ni
Cc: Dandan Bi [dandanbi]
Cc: Liming Gao [lgao4]
Cc: Debkumar De
Cc: Harry Han
Cc: Catharine West
Cc: Star Zeng
Cc: Andrew Fish
Cc: Liming Gao
Cc: Zhiguang Liu
Cc: Rebecca Cran
Cc: Peter Grehan
Signed-off-by: Ashraf Ali S
---
EmulatorPkg/Library
shraf Ali S
---
.../FspmWrapperPeim/FspmWrapperPeim.c | 25 ---
.../FspmWrapperPeim/FspmWrapperPeim.inf | 3 ++-
.../FspsWrapperPeim/FspsWrapperPeim.c | 25 ---
.../FspsWrapperPeim/FspsWrapperPeim.inf | 3 ++-
IntelFsp2Wrapp
with respect to FSP-S/M.
To Avoid Such cases separating the IA32 vs X64 is more feasible. And easily
differentiating with IA32 and X64.
Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd.
-Original Message-
From: Zeng, Star
Sent: Monday, September 27, 2021 2:15 PM
To: Chiu, Chasel
ned-off-by: Ashraf Ali S
---
.../FspmWrapperPeim/FspmWrapperPeim.c | 19 +++---
.../FspmWrapperPeim/FspmWrapperPeim.inf | 16 ++--
.../FspmWrapperPeim/IA32/FspmHelper.c | 26 +++
.../FspmWrapperPeim/X64/FspmHelper.c
ned-off-by: Ashraf Ali S
---
.../FspmWrapperPeim/FspmWrapperPeim.c | 19 +++---
.../FspmWrapperPeim/FspmWrapperPeim.inf | 16 ++--
.../FspmWrapperPeim/IA32/FspmHelper.c | 26 +++
.../FspmWrapperPeim/X64/FspmHelper.c
ned-off-by: Ashraf Ali S
---
.../FspmWrapperPeim/FspmWrapperPeim.c | 8 +++---
.../FspmWrapperPeim/FspmWrapperPeim.inf | 16 ++--
.../FspmWrapperPeim/IA32/FspmHelper.c | 26 +++
.../FspmWrapperPeim/X64/FspmHelper.c
ned-off-by: Ashraf Ali S
---
...Pkg-FSPM-S-UPD-data-address-based-on.patch | 383 ++
.../FspmWrapperPeim/FspmWrapperPeim.c | 8 +-
.../FspmWrapperPeim/FspmWrapperPeim.inf | 16 +-
.../FspmWrapperPeim/IA32/FspmHelper.c | 26 ++
.../FspmWrapperPeim/X64/Fs
ned-off-by: Ashraf Ali S
---
.../FspmWrapperPeim/FspmWrapperPeim.c | 8 +++---
.../FspmWrapperPeim/FspmWrapperPeim.inf | 16 ++--
.../FspmWrapperPeim/IA32/FspmHelper.c | 26 +++
.../FspmWrapperPeim/X64/FspmHelper.c
ned-off-by: Ashraf Ali S
---
.../FspmWrapperPeim/FspmWrapperPeim.c | 8 +++---
.../FspmWrapperPeim/FspmWrapperPeim.inf | 10 +--
.../FspmWrapperPeim/IA32/FspHelper.c | 27 +++
.../FspmWrapperPeim/X64/FspHelper.c | 27 +++
.../FspsW
ned-off-by: Ashraf Ali S
---
.../FspmWrapperPeim/FspmWrapperPeim.c | 6 +--
.../FspmWrapperPeim/FspmWrapperPeim.inf | 3 +-
.../FspsWrapperPeim/FspsWrapperPeim.c | 6 +--
.../FspsWrapperPeim/FspsWrapperPeim.inf | 1 -
.../Include/Library/FspWrapperPlatformLi
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
Cc: Kuo Ted
Cc: Duggapu Chinni B
Cc: Rangasai V Chaganty
Cc: Digant H Solanki
Cc: Sangeetha V
Cc: Ray Ni
Signed-off-by: Ashraf Ali S
---
.../FspmWrapperPeim/FspmWrapperPeim.c | 6 +--
.../FspmWrapperPeim/FspmWrapperPeim.inf
ation.
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Debkumar De
Cc: Harry Han
Cc: Catharine West
Cc: Digant H Solanki
Cc: Sangeetha V
Signed-off-by: Ashraf Ali S
---
UefiCpuPkg/SecCore/SecCoreNative.inf | 80
UefiCpuPkg/UefiCpuPkg.dsc| 1 +
2 files change
Hi., Ray
We cannot add ResetVector1G.inf in the DSC file since FILE_GUID should be the
VTF GUID.
So it's better to be added in the YAML file as we were doing for
FixupVtf/Vtf.inf.
Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd.
-Original Message-
From: Ni, Ray
Sent: Thu
Cc: Sangeetha V
Cc: Rangasai V Chaganty
Cc: Sahil Dureja
Signed-off-by: Ashraf Ali S
---
.../Vtf0/Bin/IA32/ResetVector.ia32.port80.raw | Bin 0 -> 484 bytes
.../Vtf0/Bin/IA32/ResetVector.ia32.raw| Bin 0 -> 468 bytes
.../Vtf0/Bin/IA32/ResetVector.ia32.serial.raw | Bin 0 ->
Han
Cc: Catharine West
Cc: Sangeetha V
Cc: Rangasai V Chaganty
Cc: Sahil Dureja
Signed-off-by: Ashraf Ali S
---
.../Vtf0/Bin/IA32/ResetVector.ia32.port80.raw | Bin 0 -> 484 bytes
.../Vtf0/Bin/IA32/ResetVector.ia32.raw| Bin 0 -> 468 bytes
.../Vtf0/Bin/IA32/ResetVector.ia32.seri
Han
Cc: Catharine West
Cc: Sangeetha V
Cc: Rangasai V Chaganty
Cc: Sahil Dureja
Signed-off-by: Ashraf Ali S
---
.../Vtf0/Bin/IA32/ResetVector.ia32.port80.raw | Bin 0 -> 484 bytes
.../Vtf0/Bin/IA32/ResetVector.ia32.raw| Bin 0 -> 468 bytes
.../Vtf0/Bin/IA32/ResetVector.ia32.seri
Han
Cc: Catharine West
Cc: Sangeetha V
Cc: Rangasai V Chaganty
Cc: Sahil Dureja
Signed-off-by: Ashraf Ali S
---
.../PageTable1G/ResetVector.ia32.port80.raw | Bin 0 -> 484 bytes
.../Vtf0/Bin/PageTable1G/ResetVector.ia32.raw | Bin 0 -> 468 bytes
.../PageTable1G/ResetVector.ia32.seri
works fine without any issues.
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Debkumar De
Cc: Harry Han
Cc: Catharine West
Cc: Sangeetha V
Cc: Rangasai V Chaganty
Cc: Sahil Dureja
Signed-off-by: Ashraf Ali S
---
.../PageTable1G/ResetVector.ia32.port80.raw | Bin 0 -> 484 bytes
.../Vtf0/Bin/PageTabl
works fine without any issues.
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Debkumar De
Cc: Harry Han
Cc: Catharine West
Cc: Sangeetha V
Cc: Rangasai V Chaganty
Cc: Sahil Dureja
Signed-off-by: Ashraf Ali S
---
.../PageTable1G/ResetVector.ia32.port80.raw | Bin 0 -> 484 bytes
.../Vtf0/Bin/PageTabl
Hi.,
Is this Patch Uploaded in GitHub?
Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd.
-Original Message-
From: Ni, Ray
Sent: Tuesday, July 27, 2021 10:42 AM
To: S, Ashraf Ali ; devel@edk2.groups.io
Cc: Kumar, Rahul1 ; De, Debkumar
; Han, Harry ; West, Catharine
; V
Hi.,
Based on Ray Feedback.
I have sent the patchset includes 1 and 2.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3506
Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd.
-Original Message-
From: Ni, Ray
Sent: Friday, July 23, 2021 8:03 AM
To: S, Ashraf Ali ; devel@edk2
: Ray Ni
Cc: Rahul Kumar
Cc: Debkumar De
Cc: Harry Han
Cc: Catharine West
Cc: Sangeetha V
Signed-off-by: Ashraf Ali S
---
UefiCpuPkg/ResetVector/Vtf0/Build.py | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Build.py
b/UefiCpuPkg/ResetVector
-by: Ashraf Ali S
---
UefiCpuPkg/ResetVector/Vtf0/Build.py| 6 +++---
UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py | 4 ++--
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Build.py
b/UefiCpuPkg/ResetVector/Vtf0/Build.py
Hi., Michael
Even If we generate the binaries using the Python2 also, it's getting changed.
Can you confirm from your end by generating the binaries using the build.py in
Python2
Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd.
-Original Message-
From: Kinney, Michael D
Hi. Ray
Based on Dov Murik Comments to take the python script
changes separately,
I have filed the Bugzilla for that separately.
https://bugzilla.tianocore.org/show_bug.cgi?id=3506
verified the binary. More details are in Bugzilla.
Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd
: Ray Ni
Cc: Rahul Kumar
Cc: Debkumar De
Cc: Harry Han
Cc: Catharine West
Cc: Sangeetha V
Signed-off-by: Ashraf Ali S
---
.../Vtf0/Bin/ResetVector.ia32.port80.raw | Bin 516 -> 484 bytes
.../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 468 bytes
.../Vtf0/Bin/ResetVecto
SecCoreNative and ResetVector at a same time.
3. User can choose to avoid resetvector code maintenance at the platform level.
Regards,
Ashraf Ali S
Intel Technology India Pvt. Ltd.
-Original Message-
From: Ni, Ray
Sent: Monday, July 19, 2021 8:13 AM
To: S, Ashraf Ali ; devel@edk2.groups.io
ation.
Signed-off-by: Ashraf Ali S
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Debkumar De
Cc: Harry Han
Cc: Catharine West
Cc: Digant H Solanki
Cc: Sangeetha V
---
UefiCpuPkg/SecCore/SecCoreNative.inf | 80
1 file changed, 80 insertions(+)
create mode 100644 UefiCpuPkg/Se
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3485
CacheLib EfiProgramMtrr Function takes MTRR number as a input parameter,
in the function the parameter is defined as UINTN were as the caller
calling MTTR number in UINT32.
Signed-off-by: Ashraf Ali S
Cc: Ray Ni
Cc: Chasel Chiu
Cc: Nate
.
Signed-off-by: Digant H Solanki
Cc: Ray Ni
Cc: Rangasai V Chaganty
Cc: Ashraf Ali S
---
.../Include/IndustryStandard/IgdOpRegion30.h | 100 ++
1 file changed, 100 insertions(+)
create mode 100644
Silicon/Intel/IntelSiliconPkg/Include/IndustryStandard/IgdOpRegion30.h
diff --git
ned-off-by: Ashraf Ali S
Cc: Ray Ni
Cc: Chasel Chiu
Cc: Nate DeSimone
Cc: Star Zeng
---
IntelFsp2Pkg/Tools/PatchFv.py | 18 +-
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/IntelFsp2Pkg/Tools/PatchFv.py b/IntelFsp2Pkg/Tools/PatchFv.py
index 112de4077a..eb130049b5 10
MSFT compiler can generate the map file address 8 or 16 based on which
architecture the INF is compiler. currently it's support for IA32,
modified the patchfv to support for all.
modification of few typo errors in parseModMapFile, getCurr function
required
Signed-off-by: Ashraf Ali S
Cc:
MSFT compiler can generate the map file address 8 or 16 based on which
architecture the INF is compiler. currently it's support for IA32,
modified the patchfv to support for all.
modification of few typo errors in parseModMapFile, getCurr function
required
Signed-off-by: Ashraf Ali S
Cc:
MSFT compiler can generate the map file address 8 or 16 based on which
architecture the INF is compiler. currently it's support for IA32,
modified the patchfv to support for all.
modification of few typo errors in parseModMapFile, getCurr function
required
Signed-off-by: Ashraf Ali S
Cc:
MSFT compiler can generate the map file address 8 or 16 based on which
architecture the INF is compiler. currently it's support for IA32,
it can be update the X64 in future.
modification of few typo errors in parseModMapFile, getCurr function
required
Signed-off-by: Ashraf Ali S
Cc: Ray Ni
MSFT compiler can generate the map file address 8 or 16 based on which
architecture the INF is compiler. currently it's support for IA32,
it can be update the X64 in future.
modification of few typo errors in parseModMapFile, getCurr function
required
Signed-off-by: Ashraf Ali S
Cc: Ray Ni
Signed-off-by: Ashraf Ali S
---
UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf | 1 +
1 file changed, 1 insertion(+)
diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf
b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf
index 9922cb27558c..8507275a92ae 100644
--- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.inf
+++ b
Binary accordingly.
Cc: Ray Ni
Cc: Rahul Kumar
Cc: Debkumar De
Cc: Harry Han
Cc: Catharine West
Cc: Sangeetha V
Signed-off-by: Ashraf Ali S
---
.../Vtf0/Bin/ResetVector.ia32.port80.raw | Bin 516 -> 484 bytes
.../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 468 bytes
..
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