W dniu 3.06.2024 o 18:47, Leif Lindholm via groups.io pisze:
In 2020 we got version C of spec (and then D, E, F) which allows to
use more registers:
> Allow R4—R7 (SMC32/HVC32) to be used as result registers.
> Allow X8—X17 to be used as parameter registers in SMC64/HVC64.
> Allow X4—X17
W dniu 28.05.2024 o 16:31, Ard Biesheuvel pisze:
I would expect each host bridge to have its own separate resource
windows for config space, buses and MMIO regions.
So each host bridge gets a different segment number, and each segment
is associated with a different ECAM region. That also means
EDK2/ArmPkg/Library/ArmSmcLib has code to do SMC calls.
There are ArmCallSmc[0-3]() functions for up to 3 arguments/results and
ArmCallSmc() function which can use 7 arguments and get 4 results back.
This implementation looks like version B (Nov 2016) of SMCCC
specification [1] with one more
W dniu 29.05.2024 o 15:30, Leif Lindholm via groups.io pisze:
On 2024-05-29 14:29, Marcin Juszkiewicz wrote:
Update TF-A binaries to the same version as QEMU CI uses.
Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Leif Lindholm
Thanks, pushed as 5fdbccd742d4206a2370a08c5420a1aa8c6ad85b
Update TF-A binaries to the same version as QEMU CI uses.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/Sbsa/Readme.md | 49 ---
Platform/Qemu/Sbsa/bl1.bin | Bin 23349 -> 2 bytes
Platform/Qemu/Sbsa/fip.bin | Bin 82722 -> 82722 bytes
3
Update TF-A binaries to the same version as QEMU CI uses.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/Sbsa/bl1.bin | Bin 23349 -> 2 bytes
Platform/Qemu/Sbsa/fip.bin | Bin 82722 -> 82722 bytes
2 files changed, 0 insertions(+), 0 deletions(-)
mode change 100755 => 100644
wondering where I made mistakes in handling PCIe buses.
Thanks go to Leif for pointing me to use of Aml to generate SSDT tables.
Cc: Leif Lindholm
Cc: Ard Biesheuvel
Cc: Graeme Gregory
Cc: Ray Ni
To: devel@edk2.groups.io
Signed-off-by: Marcin Juszkiewicz
---
Changes in v2:
- Dropped [WIP] status
We want to have dynaminc PCI Express variables. Which forces us to
generate MCFG from C code.
Signed-off-by: Marcin Juszkiewicz
---
Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 -
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c| 83
Silicon/Qemu/SbsaQemu
We can have more than one PCI Express bus. So instead of having static
description in DSDT we create SSDT table for each existing PCIe bus.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 2 +
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
SbsaQemu assumes that there is only one PCI Express bus. But there can
be multiple PCIe buses as NUMA systems can get 'pxb-pcie' HostBridge
devices added.
Let scan for all PCIe buses and report them back so EDK2 will be able to
find all expansions.
Signed-off-by: Marcin Juszkiewicz
W dniu 17.05.2024 o 09:17, Chao Li via groups.io pisze:
This library is copied from ArmVirtPkg, in the Arm version, the value of
PcdFlashNvStorageVariableBase, PcdFlashNvStorageFtwWorkingBase and
PcdFlashNvStorageFtwSpareBase are hardcoded in INC file.
This version will calculate them from FDT
W dniu 1.05.2024 o 19:43, Michael D Kinney via groups.io pisze:
I would like to propose that TianoCore move all code review from email
based code reviews to GitHub Pull Requests based code reviews.
The proposed date to switch would be immediately after the next stable
tag which is currently
We can have more than one PCI Express bus. So instead of having static
description in DSDT we create SSDT table for each existing PCIe bus.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 2 +
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
We want to have dynaminc PCI Express variables. Which forces us to
generate MCFG from C code.
Signed-off-by: Marcin Juszkiewicz
---
Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 -
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c| 83
Silicon/Qemu/SbsaQemu
wondering where I made mistakes in handling PCIe buses.
Thanks go to Leif for pointing me to use of Aml to generate SSDT tables.
Cc: Leif Lindholm
Cc: Ard Biesheuvel
Cc: Graeme Gregory
Cc: Ray Ni
To: devel@edk2.groups.io
Signed-off-by: Marcin Juszkiewicz
---
Marcin Juszkiewicz (3
SbsaQemu assumes that there is only one PCI Express bus. But there can
be multiple PCIe buses as NUMA systems can get 'pxb-pcie' HostBridge
devices added.
Let scan for all PCIe buses and report them back so EDK2 will be able to
find all expansions.
Signed-off-by: Marcin Juszkiewicz
FEAT_ECV for QEMU v9.0+ to get access to CNTPOFF register.
Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Leif Lindholm
Thanks!
Can you push the change yourself?
Thanks, pushed.
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent to this group.
View/Reply Online (#118233): https
The more I dig in EDK2 during SbsaQemu work, the more I see duplicated
code.
Want to scan PCI bus to check for host bridges? Two or three
implementations exist. Want to calculate checksum of just created ACPI
table? AcpiPlatformChecksum() has several, incompatible with each other,
Timer interrupts are set by ArmPkg.dec to recommended values.
We do not need to repeat it (and we missed HypVirtIntrNum one).
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 10 --
1 file changed, 10 deletions(-)
diff --git a/Platform/Qemu/SbsaQemu
() {
Remark 2173 - Creation of named objects within a method is highly
inefficient, use globals or method local variables instead ^
(\_SB.PCI0._CRS)
Simplified some _CRS nodes.
Signed-off-by: Marcin Juszkiewicz
---
Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 23 ---
1 file
I am working on some changes to SbsaQemu and got some cleanups in
meantime.
First patch gets rid of setting Pcds for Timer interrupts. ArmPkg does
it for us so we do not have to.
Second changes DSDT nodes so iasl does not complain.
Marcin Juszkiewicz (2):
SbsaQemu: do not set Timer interrupts
-by: Marcin Juszkiewicz
---
Platform/Qemu/Sbsa/Readme.md | 55 ++-
Platform/Qemu/Sbsa/bl1.bin | Bin 23365 -> 23349 bytes
Platform/Qemu/Sbsa/fip.bin | Bin 82722 -> 82722 bytes
3 files changed, 28 insertions(+), 27 deletions(-)
diff --git a/Platform/Qem
IASL complained that DSDT is not optimal:
Dsdt.
83: Name (RBUF, ResourceTemplate() {
Remark 2173 - Creation of named objects within a method is highly
inefficient, use globals or method local variables instead ^
(\_SB.USB0._CRS)
Dsdt.
377: Name (RBUF, ResourceTemplate
W dniu 16.04.2024 o 09:38, Marcin Juszkiewicz via groups.io pisze:
And if someone considers using ConfigurationManager for their platform:
please reconsider it as it may not be worth your time.
Wrote blog post about my adventure with CM:
https://marcin.juszkiewicz.com.pl/2024/04/16
W dniu 12.04.2024 o 14:43, Marcin Juszkiewicz via groups.io pisze:
W dniu 8.10.2023 o 19:25, Marcin Juszkiewicz via groups.io pisze:
I hate replying to myself after half a year of not seeing any answer. So
added some people from repo to Cc:
Can someone point me to documentation on how to use
W dniu 8.10.2023 o 19:25, Marcin Juszkiewicz via groups.io pisze:
I hate replying to myself after half a year of not seeing any answer. So
added some people from repo to Cc:
Can someone point me to documentation on how to use ACPI table
generators and ConfigurationManagerProtocol?
https
W dniu 28.03.2024 o 07:19, Xiong Yining pisze:
Add support to create SRAT(System resource affinity table) for
sbsa platform at runtime.
Signed-off-by: Xiong Yining
Reviewed-by: Marcin Juszkiewicz
Reviewed-by: Leif Lindholm
When you send a new version of patch, with changes done compared
W dniu 20.02.2024 o 08:47, Xiong Yining pisze:
Add support to create SRAT(System resource affinity table) for
sbsa platform at runtime.
Signed-off-by: Xiong Yining
Signed-off-by: Chen Baozi
Needs rebase on top of "get rid of DeviceTree from SbsaQemu" series.
Rename SbsaQemuHardwareInfoLib to
W dniu 20.02.2024 o 08:33, Xiong Yining pisze:
To support more memory nodes, we refer to the implement of
"OvmfPkg/Fdt/HighMemDxe" to add memory space for the high memory nodes
except the first one.
Signed-off-by: Xiong Yining
Signed-off-by: Chen Baozi
Needs rebase on top of "get rid of
With all changes going around sbsa-ref/QemuSbsa platform Leif suggested
that I should become maintainer as well.
My GitHub account name is "hrw".
Signed-off-by: Marcin Juszkiewicz
---
Maintainers.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Maintai
With all changes going around sbsa-ref/QemuSbsa platform Leif suggested
that I should become maintainer as well.
My GitHub account name is "hrw".
Signed-off-by: Marcin Juszkiewicz
---
Maintainers.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Maintai
From: Xiong Yining
Provide functions to check for memory information:
- amount of memory nodes
- memory address
- NUMA node id for memory
Values are read from TF-A using platform specific SMC calls.
Signed-off-by: Xiong Yining
Signed-off-by: Chen Baozi
Signed-off-by: Marcin Juszkiewicz
We have SbsaQemuHardwareInfoLib to ask for hardware details. No need to
parse DeviceTree anymore.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf | 6 ++
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 5 ++---
.../SbsaQemu/Library
There is no need for EDK2 to know that there is DeviceTree around.
All hardware information is read using functions from
SbsaQemuHardwareInfoLib library.
Signed-off-by: Marcin Juszkiewicz
---
Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 1 -
Platform/Qemu/SbsaQemu/SbsaQemu.dsc
This library provides functions to check for hardware information.
For now it covers CPU ones:
- amount of cpu cores
- MPIDR value for cpu core
- NUMA node id for cpu core
Values are read from TF-A using platform specific SMC calls.
Signed-off-by: Marcin Juszkiewicz
---
Silicon/Qemu/SbsaQemu
for handling SMC stuff. There is no DT parsing
anywhere.
TF-A part is merged already (and we have it in edk2-non-osi):
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/25707
Patch 4 needs work to pass MemInfo as reference.
Signed-off-by: Marcin Juszkiewicz
---
Changes in v9:
- recreated
From: Xiong Yining
Provide functions to check for memory information:
- amount of memory nodes
- memory address
- NUMA node id for memory
Values are read from TF-A using platform specific SMC calls.
Signed-off-by: Xiong Yining
Signed-off-by: Chen Baozi
Signed-off-by: Marcin Juszkiewicz
We have SbsaQemuHardwareInfoLib to ask for hardware details. No need to
parse DeviceTree anymore.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf | 6 ++
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 5 ++---
.../SbsaQemu/Library
There is no need for EDK2 to know that there is DeviceTree around.
All hardware information is read using functions from
SbsaQemuHardwareInfoLib library.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 1 -
1 file changed, 1 deletion(-)
diff --git a/Platform/Qemu
This library provides functions to check for hardware information.
For now it covers CPU ones:
- amount of cpu cores
- MPIDR value for cpu core
- NUMA node id for cpu core
Values are read from TF-A using platform specific SMC calls.
Signed-off-by: Marcin Juszkiewicz
---
Silicon/Qemu/SbsaQemu
for handling SMC stuff. There is no DT parsing
anywhere.
TF-A part is merged already (and we have it in edk2-non-osi):
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/25707
Patch 4 needs work to pass MemInfo as reference.
Signed-off-by: Marcin Juszkiewicz
---
Changes in v8:
- added
W dniu 19.03.2024 o 17:53, Ard Biesheuvel pisze:
new file mode 100644
index ..e621c422bd40
--- /dev/null
+++
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf
@@ -0,0 +1,31 @@
+#/* @file
+#
+# Copyright (c) 2024, Linaro Ltd. All rights reserved.
+#
From: Xiong Yining
Provide functions to check for memory information:
- amount of memory nodes
- memory address
- NUMA node id for memory
Values are read from TF-A using platform specific SMC calls.
Signed-off-by: Xiong Yining
Signed-off-by: Chen Baozi
Signed-off-by: Marcin Juszkiewicz
There is no need for EDK2 to know that there is DeviceTree around.
All hardware information is read using functions from
SbsaQemuHardwareInfoLib library.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 1 -
.../SbsaQemu/Library/FdtHelperLib
We have SbsaQemuHardwareInfoLib to ask for hardware details. No need to
parse DeviceTree anymore.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf | 6 ++
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 5 ++---
.../SbsaQemu/Library
This library provides functions to check for hardware information.
For now it covers CPU ones:
- amount of cpu cores
- MPIDR value for cpu core
- NUMA node id for cpu core
Values are read from TF-A using platform specific SMC calls.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu
for handling SMC stuff. There is no DT parsing
anywhere.
TF-A part is merged already (and we have it in edk2-non-osi):
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/25707
Patch 4 needs work to pass MemInfo as reference.
Signed-off-by: Marcin Juszkiewicz
---
Changes in v7:
- dropped
W dniu 19.03.2024 o 12:02, Ard Biesheuvel pisze:
EDK2 starts and one of the first DXE called is SbsaQemuPlatformDxe one:
How is this guaranteed? DXE are generally dispatched in the order in
which they appear in the FDF, but only if all DEPEX dependencies are
satisfied. DEPEXes are compiled
W dniu 15.03.2024 o 12:49, Marcin Juszkiewicz pisze:
W dniu 14.03.2024 o 16:13, Ard Biesheuvel pisze:
How is it guaranteed that other components will only see the correct
core count? DXE dispatch is ordered using a dependency graph, so all
users of this PCD should never execute before
W dniu 14.03.2024 o 16:13, Ard Biesheuvel pisze:
+++ b/Silicon/Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf
@@ -1,7 +1,7 @@
## @file
# This driver effectuates SbsaQemu platform configuration settings
#
-# Copyright (c) 2019, Linaro Ltd. All rights reserved.
+#
W dniu 14.03.2024 o 16:14, Ard Biesheuvel pisze:
+++
b/Silicon/Qemu/SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf
@@ -0,0 +1,32 @@
+#/* @file
+#
+# Copyright (c) Linaro Ltd. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+#*/
+
+[Defines]
+
W dniu 14.03.2024 o 15:17, Marcin Juszkiewicz via groups.io pisze:
We want to stop parsing DeviceTree (in EDK2) to gather hardware information.
Instead we ask TF-A for those details using SMC calls. On real hardware
platform it could be asking on-board Embedded Controller.
Hardware information
ing features for qemu_sbsa platform are
merged upstream and included in the build:
-commit 408cde8a59080ac2caa11c4d99474b2ef09f90df
+commit 42925c15bee09162c6dfc8c2204843ffac6201c1
Author: Marcin Juszkiewicz
-Date: Mon Sep 18 12:47:45 2023 +0200
+Date: Tue Nov 21 14:53:26 2023 +0100
-fi
From: Xiong Yining
Add the DeviceTree fallbacks to parsing the information about memory
if the related SMC calls Failed.
Signed-off-by: Xiong Yining
Signed-off-by: Chen Baozi
---
.../SbsaQemuHardwareInfoLib.c | 106 +++-
1 file changed, 104
From: Xiong Yining
Provide functions to check for memory information:
- amount of memory nodes
- memory address
- NUMA node id for memory
Values are read from TF-A using platform specific SMC calls.
Signed-off-by: Xiong Yining
Signed-off-by: Chen Baozi
---
There is no need for EDK2 to know that there is DeviceTree around.
All hardware information is read using functions from
SbsaQemuHardwareInfoLib library.
Library fallbacks to parsing DT if needed.
Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Leif Lindholm
---
Platform/Qemu/SbsaQemu
In case we do not have cpu information (SMC call fails,
our minimal DT lacks info) we shutdown system.
Signed-off-by: Marcin Juszkiewicz
---
.../Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf| 2 ++
.../SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c | 3
During platform initialization we read amount of cpu cores and set
PcdCoreCount so there is no need to call FdtHandler.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf | 6 ++
Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c
We read it once and store in Pcd for future use.
Signed-off-by: Marcin Juszkiewicz
---
.../SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf | 4 +++-
.../SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c | 9 +
2 files changed, 8 insertions(+), 5 deletions
Signed-off-by: Marcin Juszkiewicz
---
Changes in v6 (Marcin Juszkiewicz):
- patch 5 now shutdowns system in case of no CPU information
Changes in v5 (Xiong Yining):
- added missing patch
- Link to v5:
https://openfw.io/edk2-devel/20240131132400.3022662-1-xiongyining1...@phytium.com.cn/
Changes
This library provides functions to check for hardware information.
For now it covers CPU ones:
- amount of cpu cores
- MPIDR value for cpu core
- NUMA node id for cpu core
Values are read from TF-A using platform specific SMC calls.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu
er.arm.com/documentation/ddi0601/2023-12/
While I can keep them in my application, they may be useful for someone
else too.
ArmLib build requirements need bump to 'armv8-a+sme' to get access to
SVE/SME related system registers.
Marcin Juszkiewicz (2):
ArmPkg/ArmLib: Add functions to read SVE/SME system
https://developer.arm.com/documentation/ddi0601/2023-12/ lists
more system registers than EDK2 supports now.
ISAR3, MMFR3, MMFR4, PFR2, FPFR0 were added.
Signed-off-by: Marcin Juszkiewicz
---
ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h| 34 ---
.../Library/ArmLib/AArch64
Signed-off-by: Marcin Juszkiewicz
---
ArmPkg/Library/ArmLib/ArmBaseLib.inf | 4
ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h | 12
ArmPkg/Library/ArmLib/AArch64/AArch64Support.S | 11 +++
3 files changed, 27 insertions(+)
diff --git a/ArmPkg/Library/ArmLib/ArmBase
W dniu 20.02.2024 o 8:33 AM, Xiong Yining pisze:
To support more memory nodes, we refer to the implement of
"OvmfPkg/Fdt/HighMemDxe" to add memory space for the high memory nodes
except the first one.
Signed-off-by: Xiong Yining
Signed-off-by: Chen Baozi
Tested-by: Marcin Juszkiew
W dniu 20.02.2024 o 9:03 AM, Xiong Yining pisze:
This is beacuse UEFI only allocates the first memory node memory space
for SbsaQemu platform, i refer to implemet of "OvmfPkg/Fdt/HighMemDxe"
and add the support for other memory nodes via GCD services. Maybe you
can apply patch "support multi
W dniu 21.02.2024 o 2:49 AM, Nate DeSimone pisze:
I would like to remind everyone that we generally don't accept
submissions via PRs yet. At the very least please click "Rebase and
merge" when closing the PR instead of "Merge pull request". Since that
merge commit is currently at the top of the
W dniu 31.01.2024 o 2:15 PM, Xiong Yining pisze:
Add support to create SRAT(System resource affinity table) for
sbsa platform at runtime.
Signed-off-by: Xiong Yining
Signed-off-by: Chen Baozi
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h | 27 ++
this change the only place where DT data is parsed directly is
checking for memory nodes. Patches for that code will be sent once we
get SMC calls into TF-A.
Signed-off-by: Marcin Juszkiewicz
---
Changes in v3:
- added SMC_SIP_CALL_SUCCESS
- on SMC call fail tell that SMC call failed instead
There is no need for EDK2 to know that there is DeviceTree around.
All hardware information is read using functions from
SbsaQemuHardwareInfoLib library.
Library fallbacks to parsing DT if needed (used with too old TF-A).
Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Leif Lindholm
In case we do not have cpu information (SMC call fails,
our minimal DT lacks info) we hang.
TODO: shutdown instead
Signed-off-by: Marcin Juszkiewicz
---
.../SbsaQemu/Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c | 3 +++
1 file changed, 3 insertions(+)
diff --git
a/Silicon/Qemu
During platform initialization we read amount of cpu cores and set
PcdCoreCount so there is no need to call FdtHandler.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf | 6 ++
Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c
We read it once and store in Pcd for future use.
Signed-off-by: Marcin Juszkiewicz
---
.../SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf | 4 +++-
.../SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c | 9 +
2 files changed, 8 insertions(+), 5 deletions
This library provides functions to check for hardware information.
For now it covers CPU ones:
- amount of cpu cores
- MPIDR value for cpu core
- NUMA node id for cpu core
Values are read from TF-A using platform specific SMC calls.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu
W dniu 19.01.2024 o 20:20, Leif Lindholm pisze:
On Tue, Jan 16, 2024 at 08:48:34 +0100, Marcin Juszkiewicz wrote:
During platform initialization we read amount of cpu cores and set
PcdCoreCount so there is no need to call FdtHandler.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu
W dniu 19.01.2024 o 20:18, Leif Lindholm pisze:
On Tue, Jan 16, 2024 at 08:48:32 +0100, Marcin Juszkiewicz wrote:
This library provides functions to check for hardware information.
For now it covers CPU ones:
- amount of cpu cores
- MPIDR value for cpu core
- NUMA node id for cpu core
Values
We emulate XHCI controller already. No need to add it.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/Readme.md | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Platform/Qemu/SbsaQemu/Readme.md b/Platform/Qemu/SbsaQemu/Readme.md
index 3355adebd4c6
There is no need for EDK2 to know that there is DeviceTree around.
All hardware information is read using functions from
SbsaQemuHardwareInfoLib library.
Library fallbacks to parsing DT if needed (used with too old TF-A).
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu
During platform initialization we read amount of cpu cores and set
PcdCoreCount so there is no need to call FdtHandler.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf | 6 ++
Platform/Qemu/SbsaQemu/OemMiscLib/OemMiscLib.c
This library provides functions to check for hardware information.
For now it covers CPU ones:
- amount of cpu cores
- MPIDR value for cpu core
- NUMA node id for cpu core
Values are read from TF-A using platform specific SMC calls.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu
this change the only place where DT data is parsed directly is
checking for memory nodes. Patches for that code will be sent once we
get SMC calls into TF-A.
Signed-off-by: Marcin Juszkiewicz
---
Marcin Juszkiewicz (4):
Platform/SbsaQemu: add SbsaQemuHardwareInfoLib
Platform/SbsaQemu
We read it once and store in Pcd for future use.
Signed-off-by: Marcin Juszkiewicz
---
.../SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf | 4 +++-
.../SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c | 9 +
2 files changed, 8 insertions(+), 5 deletions
W dniu 15.01.2024 o 19:02, Leif Lindholm pisze:
As part of removing DeviceTree use we moved cpu related parts to TF-A.
On EDK2 side we get values via SMC calls during platform initialization.
Could you split this into three patches?:
- Adding new Library (Library name should have a Lib
.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 4 +-
.../Qemu/SbsaQemu/OemMiscLib/OemMiscLib.inf | 6 +-
.../SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf | 4 +-
.../SbsaQemuPlatformDxe.inf | 4 +-
.../Library/FdtHelperLib
to parsing DeviceTree data directly. Just now
it is present in one place together with new code for handling SMC
stuff.
TF-A part: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/25707
Marcin Juszkiewicz (1):
SbsaQemu: get cpu information from TF-A
Platform/Qemu/SbsaQemu
W dniu 4.12.2023 o 13:58, Ard Biesheuvel pisze:
On Mon, 4 Dec 2023 at 13:38, Alexander Graf wrote:
On 04.12.23 13:20, Gerd Hoffmann wrote:
I don't think it helps to go off on a tangent about why shim exists
and why it is so terrible, as I don't think there is actually any
disagreement about
-by: Marcin Juszkiewicz
---
Platform/Qemu/Sbsa/bl1.bin | Bin 22933 -> 23029 bytes
Platform/Qemu/Sbsa/fip.bin | Bin 82722 -> 82722 bytes
2 files changed, 0 insertions(+), 0 deletions(-)
mode change 100755 => 100644 Platform/Qemu/Sbsa/bl1.bin
diff --git a/Platform/Qemu/Sbsa/bl1.bin b/Plat
W dniu 22.11.2023 o 13:26, Leif Lindholm pisze:
On 2023-11-22 11:11, Sami Mujawar wrote:
[SAMI] The proposal above looks good to me. This may be slightly
off topic, but can we also enable edk2-platform upstream CI as
well, please? This would be helpful to catch issues much earlier.
[/SAMI]
Signed-off-by: Marcin Juszkiewicz
---
Maintainers.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Maintainers.txt b/Maintainers.txt
index affb2632e0db..7bfd3c850a30 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -407,7 +407,7 @@ M: Daniel Schaefer
Phytium
cessor architecture specific
> discovery mechanisms should be used to ascertain the value of this
> attribute.
Signed-off-by: Marcin Juszkiewicz
---
Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 2 +-
Platform/RaspberryPi/AcpiTables/Pptt.aslc | 2 +-
Sil
W dniu 13.11.2023 o 12:58, Laszlo Ersek pisze:
Note that 73.0.3 indents the subexpression to the "//" comment on the
previous line, while 73.0.8 ignores the comment -- which I think is
justified here.
I believe this improvement may come from uncrustify commit 239c4fad745b
("Prevent endless
We want to check "if platver < 0.3" in an easy way.
Signed-off-by: Marcin Juszkiewicz
---
.../IndustryStandard/SbsaQemuPlatformVersion.h | 25
1 file changed, 25 insertions(+)
diff --git
a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard/SbsaQemuPlatfor
We need platform version to be at least 0.3 to have XHCI
in virtual hardware. On older platforms there is non-working
EHCI which we ignore.
Set DSDT node to be disabled so operating system will not try
to initialize not-existing hardware.
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers
We need platform version to be at least 0.3 to have XHCI
in virtual hardware. On older platforms there is non-working
EHCI which we ignore.
Signed-off-by: Marcin Juszkiewicz
---
.../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c| 49 +++-
1 file changed, 27 insertions(+), 22
It will be needed for playing with disabling XHCI later.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
b/Platform/Qemu/SbsaQemu/SbsaQemu.dsc
index 806651fc55a0..fa85bd8dab89
platforms
- no SSDT overlays for EHCI/XHCI
- no EHCI at all (it does not work anyway)
- no Pcd renaming
---
Marcin Juszkiewicz (4):
SbsaQemu: introduce macro to compare platform version
SbsaQemu: add AcpiLib
SbsaQemu: initialize XHCI only if it exists
SbsaQemu: disable XH
W dniu 18.10.2023 o 15:36, Laszlo Ersek pisze:
EDK2 expects some random version of uncrustify.
It is not part of BaseTools so I use upstream version. And it looks like
they format in different way using the same config file.
Project URL (to clone and build):
190: Device (PCI0) Warning 3073 -
Multiple types ^ (Device object requires either a _HID or _ADR, but not both)
PCI Firmware specification does not require _ADR for Host bridges.
Signed-off-by: Marcin Juszkiewicz
---
Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 1 -
1 file changed, 1
We need platform version to be at least 0.3 to have XHCI
in virtual hardware. On older platforms there is non-working
EHCI which we ignore.
Set DSDT node to be disabled so operating system will not try
to initialize not-existing hardware.
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers
We need platform version to be at least 0.3 to have XHCI
in virtual hardware. On older platforms there is non-working
EHCI which we ignore.
Signed-off-by: Marcin Juszkiewicz
---
.../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.c| 49 +++-
1 file changed, 27 insertions(+), 22
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