W dniu 7.11.2024 o 13:04, Jonathan Cameron pisze:
On Tue, 5 Nov 2024 18:43:46 +0800
"Yuquan Wang" wrote:
This creates a default pxb-cxl (bus_nr=0xc0) bridge with two
cxl root ports on sbsa-ref. And the memory layout places 64K
space for the cxl host bridge register regions(CHBCR) in the
sbsa-r
I looked at pull requests for edk2-platforms yesterday. Went through
those from times when we used only mail for patches.
Closed several ones as their code was already merged, left "please
rebase or close" like comments in those which require work.
Repo went from 44 to 26 open pull requests.
On 3.09.2024 23:41, Michael D Kinney via groups.io wrote:
Pushed as 4f49a843ff..f709251f5b
I did pull request then for sbsaqemu fix. Github action [1] failed:
Failed to create token for "edk2-platforms" (attempt 1): Not Found -
https://docs.github.com/rest/apps/apps#get-a-repository-installat
On 30.08.2024 16:36, Rebecca Cran wrote:
Do the TF-A binaries in edk2-non-osi need updated for SbsaQemu?
With the binaries in Platform/Qemu/Sbsa I get the following error during
boot:
GetCpuCount: We have 4 cpus.
GetMpidr: MPIDR for CPU0: = 0
GetMpidr: MPIDR for CPU1: = 1
GetMpidr: MPIDR for
EDK2 requires SIP_SVC_GET_CPU_TOPOLOGY call nowadays. Bump binaries to
provide it.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/Sbsa/Readme.md | 15 ++-
Platform/Qemu/Sbsa/bl1.bin | Bin 2 -> 2 bytes
Platform/Qemu/Sbsa/fip.bin | Bin 82722 -> 82722 bytes
3
of ArmMonitorLib to simplify code.
First patch also moves all SMC calls we use into HardwareInfoLib to have
all hardware related queries in one place.
Signed-off-by: Marcin Juszkiewicz
For the series:
Leif Lindholm
Thanks!
Thanks, pushed as 22ed007688b181a7682e4f82ae4537def48186c0
SbsaQemuPlatformDxe does not need ArmVirtPkg and EmbeddedPkg.
SbsaHardwareInfoLib does not need EmbeddedPkg.
Signed-off-by: Marcin Juszkiewicz
---
.../Qemu/SbsaQemu/Drivers/SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf | 2 --
.../Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.inf
ArmMonitorLib allows to use 18 registers are both arguments and results.
Signed-off-by: Marcin Juszkiewicz
---
.../SbsaQemuHardwareInfoLib.inf | 2 +-
.../SbsaQemuHardwareInfoLib.c| 75 ++--
2 files changed, 37 insertions(+), 40
We now have HardwareInfo library so let move all hardware queries there.
Signed-off-by: Marcin Juszkiewicz
---
.../SbsaQemuPlatformDxe/SbsaQemuPlatformDxe.inf | 2 +-
.../SbsaQemuHardwareInfoLib.inf | 5 ++
.../Qemu/SbsaQemu/Include/Library/HardwareInfoLib.h | 31
moves all SMC calls we use into HardwareInfoLib to have
all hardware related queries in one place.
Signed-off-by: Marcin Juszkiewicz
---
Marcin Juszkiewicz (3):
SbsaQemu: move SMC calls to HardwareInfoLib
SbsaQemu: move from ArmSmcLib to ArmMonitorLib
SbsaQemu: drop not needed
merged:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/27189
Signed-off-by: Xiong Yining
Signed-off-by: Marcin Juszkiewicz
For the series:
Reviewed-by: Leif Lindholm
Thanks!
Thanks.
Pushed as f30a670e507712794b04f9c360467ba329c1f381
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You
Function AddPpttTable() adding PPTT got too long. This change moves part
of it into helper function AddCoresToPpttTable() which takes care of
generating entries for Core and below (Cache, Thread).
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 243
: Marcin Juszkiewicz
---
.../SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 32 +-
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c| 45
2 files changed, 55 insertions(+), 22 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard
-> Cores -> Caches + Threads (if exist)
Cache sizes are still 32+32+512KB (L1d, L1i, L2).
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c| 50 ++--
1 file changed, 26 insertions(+), 24 deletions(-)
diff --git a/Silicon
-off-by: Xiong Yining
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h | 11 ++
.../Include/IndustryStandard/SbsaQemuAcpi.h | 32
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 195
3 files changed, 166 insertions
ACPI 6.5 is the newest version of specification so far. The only
functional change to make is handling of CacheId (has to be unique and
higher than zero).
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h | 4 +-
.../Include/IndustryStandard
,
clusters and cores are read from TF-A using platform specific SMC call.
Number of threads is caluculated using the cpu count and the number of
sockets, clusters and cores.
Signed-off-by: Xiong Yining
Signed-off-by: Marcin Juszkiewicz
---
.../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h | 1
-firmware-a/+/27189
Signed-off-by: Xiong Yining
Signed-off-by: Marcin Juszkiewicz
To: devel@edk2.groups.io
Cc: Leif Lindholm
Cc: Ard Biesheuvel
Cc: Graeme Gregory
Cc: Chen Baozi
Cc: Xiong Yining
Cc: Jonathan Cameron
Changes in v6:
- use ArmMonitorLib for GetCpuTopology() as we need 5 return
-by: Ard Biesheuvel
For Qemu/SbsaQemu:
Reviewed-by: Marcin Juszkiewicz
SbsaQemu does not boot without this patch applied:
UEFI firmware (version 1.0 built at 21:12:07 on Aug 5 2024)
add-symbol-file
/home/marcin/devel/linaro/sbsa-qemu/code/Build/SbsaQemu/DEBUG_CLANGDWARF/AARCH64/ArmPlatformPkg
.groups.io
Cc: Leif Lindholm
Cc: Ard Biesheuvel
Cc: Graeme Gregory
Signed-off-by: Marcin Juszkiewicz
---
Marcin Juszkiewicz (2):
SbsaQemu: fix comments in SbsaQemuHardwareInfoLib
SbsaQemu: drop not used Pcds for Cluster/Core count
Reviewed-by: Ard Biesheuvel
Thanks, pushed as
K2 to make PcdProcessorVersion dynamic.
Signed-off-by: Marcin Juszkiewicz
I am going to make the same remark as I did before in a different
context: how is it guaranteed that the code that sets the PCD executes
before the code that consumes it?
Making PCDs dynamic is usually not the solution here, unless they
SbsaQemu platform have several cpu models available. Since start it
reported "arm-virt" one in SMBIOS instead of real one.
This change replaces it with the real cpu model like Cortex-A57,
Neoverse-N2 etc.
Requires change in EDK2 to make PcdProcessorVersion dynamic.
Signed-off-
On SbsaQemu platform we would like to be able to set this variable
during bootup as cpu model can be different on each system run.
Signed-off-by: Marcin Juszkiewicz
---
ArmPkg/ArmPkg.dec | 2 +-
.../Universal/Smbios/ProcessorSubClassDxe
R and sets
cpu model name.
Marcin Juszkiewicz (2):
ArmPkg: make PcdProcessorVersion dynamic
SbsaQemu: set CPU model in SMBIOS
ArmPkg/ArmPkg.dec | 2 +-
.../Universal/Smbios/ProcessorSubClassDxe/ProcessorSubClass.c | 4 ++--
2 files changed, 3 insert
-off-by: Xiong Yining
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h | 11 ++
.../Include/IndustryStandard/SbsaQemuAcpi.h | 32
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 195
3 files changed, 166 insertions
: Marcin Juszkiewicz
---
.../SbsaQemu/Include/IndustryStandard/SbsaQemuAcpi.h | 32 +-
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c| 45
2 files changed, 55 insertions(+), 22 deletions(-)
diff --git a/Silicon/Qemu/SbsaQemu/Include/IndustryStandard
Function AddPpttTable() adding PPTT got too long. This change moves part
of it into helper function AddCoresToPpttTable() which takes care of
generating entries for Core and below (Cache, Thread).
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 243
-> Cores -> Caches + Threads (if exist)
Cache sizes are still 32+32+512KB (L1d, L1i, L2) as QEMU does not
implement them at all so we can tell whatever.
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c| 50 ++--
1 file changed, 2
ACPI 6.5 is the newest version of specification so far. The only
functional change to make is handling of CacheId (has to be unique and
higher than zero).
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h | 4 +-
.../Include/IndustryStandard
-firmware-a/+/27189
Signed-off-by: Xiong Yining
Signed-off-by: Marcin Juszkiewicz
To: devel@edk2.groups.io
Cc: Leif Lindholm
Cc: Ard Biesheuvel
Cc: Graeme Gregory
Cc: Chen Baozi
Cc: Xiong Yining
Cc: Jonathan Cameron
Changes in v5:
- added support for cache sizes on cores with FEAT_CCIDX
,
clusters and cores are read from TF-A using platform specific SMC call.
Number of threads is caluculated using the cpu count and the number of
sockets, clusters and cores.
Signed-off-by: Xiong Yining
Signed-off-by: Marcin Juszkiewicz
---
.../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h | 1
On 10.07.2024 19:52, Marcin Juszkiewicz via groups.io wrote:
We were exporting fake cpu cache values instead of reading them from
CCSIDR registers.
This change gets rid of fake values in favour of existing ones.
Code taken from Ampere platform core.
Reported-by: Jonathan Cameron
Signed-off-by
We read CPU topology from TF-A so there is no need to keep fake values
anymore.
Signed-off-by: Marcin Juszkiewicz
---
Silicon/Qemu/SbsaQemu/SbsaQemu.dec| 3 ---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 4
Silicon/Qemu/SbsaQemu
EDK2 takes information from TF-A. How it got that info does not interest
us.
Signed-off-by: Marcin Juszkiewicz
---
.../Library/SbsaQemuHardwareInfoLib/SbsaQemuHardwareInfoLib.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
a/Silicon/Qemu/SbsaQemu/Library
Cc: Graeme Gregory
Signed-off-by: Marcin Juszkiewicz
---
Marcin Juszkiewicz (2):
SbsaQemu: fix comments in SbsaQemuHardwareInfoLib
SbsaQemu: drop not used Pcds for Cluster/Core count
Silicon/Qemu/SbsaQemu/SbsaQemu.dec | 3 ---
Platform/Qemu/SbsaQemu
-> Cores -> Caches + Threads (if exist)
Cache sizes are still 32+32+512KB (L1d, L1i, L2) as QEMU does not
implement them at all so we can tell whatever.
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c| 50 ++--
1 file changed, 2
We were exporting fake cpu cache values instead of reading them from
CCSIDR registers.
This change gets rid of fake values in favour of existing ones.
Code taken from Ampere platform core.
Reported-by: Jonathan Cameron
Signed-off-by: Marcin Juszkiewicz
---
.../SbsaQemu/Include
-off-by: Xiong Yining
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h | 11 ++
.../Include/IndustryStandard/SbsaQemuAcpi.h | 32
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 195
3 files changed, 166 insertions
Function AddPpttTable() adding PPTT got too long. This change moves part
of it into helper function AddCoresToPpttTable() which takes care of
generating entries for Core and below (Cache, Thread).
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 243
ACPI 6.5 is the newest version of specification so far. The only
functional change to make is handling of CacheId (has to be unique and
higher than zero).
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h | 4 +-
.../Include/IndustryStandard
,
clusters and cores are read from TF-A using platform specific SMC call.
Number of threads is caluculated using the cpu count and the number of
sockets, clusters and cores.
Signed-off-by: Xiong Yining
Signed-off-by: Marcin Juszkiewicz
---
.../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h | 1
-firmware-a/+/27189
Signed-off-by: Xiong Yining
Signed-off-by: Marcin Juszkiewicz
To: devel@edk2.groups.io
Cc: Leif Lindholm
Cc: Ard Biesheuvel
Cc: Graeme Gregory
Cc: Chen Baozi
Cc: Xiong Yining
Cc: Jonathan Cameron
Changes in v4:
- renamed all *Index variables to *Offset ones for clarity
Dnia wtorek, 9 lipca 2024 15:00:12 CEST Leif Lindholm via groups.io pisze:
> On Tue, Jul 09, 2024 at 12:47:10 +0200, Marcin Juszkiewicz wrote:
> > Function AddPpttTable() adding PPTT got too long. This change moves part
> > of it into helper function AddCoresToPpttTable() whic
,
clusters and cores are read from TF-A using platform specific SMC call.
Number of threads is caluculated using the cpu count and the number of
sockets, clusters and cores.
Signed-off-by: Xiong Yining
Signed-off-by: Marcin Juszkiewicz
---
.../SbsaQemu/Include/IndustryStandard/SbsaQemuSmc.h | 1
-off-by: Xiong Yining
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h | 11 ++
.../Include/IndustryStandard/SbsaQemuAcpi.h | 32
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 187 +++-
3 files changed, 158 insertions
-> Cores -> Caches + Threads (if exist)
Cache sizes are still 32+32+512KB (L1d, L1i, L2) as QEMU does not
implement them at all so we can tell whatever.
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c| 47 +++-
1 file changed, 2
Function AddPpttTable() adding PPTT got too long. This change moves part
of it into helper function AddCoresToPpttTable() which takes care of
generating entries for Core and below (Cache, Thread).
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 237
ACPI 6.5 is the newest version of specification so far. The only change
to make is handling of CacheId (has to be unique and higher than zero).
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h | 4 +-
.../Include/IndustryStandard/SbsaQemuAcpi.h
-firmware-a/+/27189
Signed-off-by: Xiong Yining
Signed-off-by: Marcin Juszkiewicz
To: devel@edk2.groups.io
Cc: Leif Lindholm
Cc: Ard Biesheuvel
Cc: Graeme Gregory
Cc: Chen Baozi
Cc: Xiong Yining
Changes in v3:
- split ACPI 6.5 changes into separate patch
- moved adding cores/threads to separate
sulting in the same situation as before.
> >
> > TRNG is not implemented in TCG mode but is required by RngDxe to run.
> >
> > On older cpu cores nothing changes.
> >
> > Signed-off-by: Marcin Juszkiewicz
>
> Thanks!
>
ed by both Neoverse-N2 and 'max' cpu implemented by QEMU.
Other cpu models lack it which prevents the RngDxe driver from running,
resulting in the same situation as before.
TRNG is not implemented in TCG mode but is required by RngDxe to run.
On older cpu cores nothing changes.
Signed-off-by
: Xiong Yining
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.h | 17 +-
.../Include/IndustryStandard/SbsaQemuAcpi.h | 78 +++-
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c | 190 +++-
3 files changed, 180 insertions
-> Cores -> Caches + Threads (if exist)
Cache sizes are still 32+32+512KB (L1d, L1i, L2) as QEMU does not
implement them at all so we can tell whatever.
Signed-off-by: Marcin Juszkiewicz
---
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c| 46 ++--
1 file changed, 2
and cores are read from TF-A using platform
specific SMC calls. And the number of threads is caluculated
using the total number of cpus and the number of sockets,
clusters and cores.
Signed-off-by: Xiong Yining
Signed-off-by: Marcin Juszkiewicz
---
.../SbsaQemu/Include/IndustryStandard
-firmware-a/+/27189
Signed-off-by: Xiong Yining
Signed-off-by: Marcin Juszkiewicz
Changes since v1 (Marcin Juszkiewicz):
- use ACPI 6.5 structures (instead of 6.3)
- add patch to move cache data to cores (instead of clusters)
- this is for future MPAM support
- reformatted sources using uncrustify
W dniu 1.07.2024 o 13:08, Leif Lindholm pisze:
On 2024-06-27 15:22, Marcin Juszkiewicz wrote:
By default we have Neoverse-N2 cpu which supports FEAT_RNG feature.
Commit 5de5e230a80bed083360da95ba16a2c4a001620d (in EDK2) enabled that
for
ArmVirt platform.
RNDR is implemented by both Neoverse
Dxe driver from running,
resulting in the same situation as before.
TRNG is not implemented in TCG mode but is required by RngDxe to run.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 +-
Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 1 +
2 files changed, 6 insert
7; device in QEMU to have some TRNG emulated.
Signed-off-by: Marcin Juszkiewicz
Marcin Juszkiewicz (1):
SbsaQemu: use FEAT_RNG for EFI_RNG_PROTOCOL
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 6 +-
Platform/Qemu/SbsaQemu/SbsaQemu.fdf | 1 +
2 files changed, 6 insertions
W dniu 25.06.2024 o 20:04, Leif Lindholm pisze:
Makes sense.
If you change the new version to 2024 instead of 2023 :)
Oops. Fixed.
Reviewed-by: Leif Lindholm
Thanks, pushed as feff6a709d5d4d392f4f34529b909e2c4176fa33
-=-=-=-=-=-=-=-=-=-=-=-
Groups.io Links: You receive all messages sent
Lot of time passed since 10th of August 2020 when this platform was
added to EDK2-platforms repository.
So let bump PcdAcpiDefaultOemRevision value to today. So everyone will
see during OS boot that things are changing.
Signed-off-by: Marcin Juszkiewicz
---
Silicon/Qemu/SbsaQemu/Acpi.dsc.inc
W dniu 25.06.2024 o 12:41, Marcin Juszkiewicz via groups.io pisze:
W dniu 25.06.2024 o 12:40, Marcin Juszkiewicz via groups.io pisze:
My work on EDK2 is only around SBSA Reference Platform (QemuSbsa)
which is software emulated machine. And from time to time there are
moments when I am
W dniu 25.06.2024 o 12:40, Marcin Juszkiewicz via groups.io pisze:
My work on EDK2 is only around SBSA Reference Platform (QemuSbsa) which
is software emulated machine. And from time to time there are moments
when I am wondering on getting some physical system which runs EDK2 to
have system
My work on EDK2 is only around SBSA Reference Platform (QemuSbsa) which
is software emulated machine. And from time to time there are moments
when I am wondering on getting some physical system which runs EDK2 to
have system for experiments.
Can someone recommend some hardware?
It does not ma
W dniu 22.06.2024 o 20:04, Rebecca Cran pisze:
I decided to do some testing around the cost of copying vs
decompressing and moved all the drivers in SbsaQemu into the
uncompressed section (as described in
https://github.com/tianocore/tianocore.github.io/wiki/ArmPkg-Compression),
but firmware bu
W dniu 22.06.2024 o 15:18, Leif Lindholm via groups.io pisze:
On Fri, Jun 21, 2024 at 16:04:07 +0200, Marcin Juszkiewicz wrote:
uncrustify is required in EDK2 repository. SbsaQemu (and other platforms
in edk2-platforms) code was free from using it IIRC.
Reformat all files to make new
uncrustify is required in EDK2 repository. SbsaQemu (and other platforms
in edk2-platforms) code was free from using it IIRC.
Reformat all files to make new contributions easier. We can recommend
formatting sources without generating extra work for developers.
Signed-off-by: Marcin Juszkiewicz
uncrustify is required in EDK2 repository. SbsaQemu (and other platforms
in edk2-platforms) code was free from using it IIRC.
Reformat all files to make new contributions easier. We can recommend
formatting sources without generating extra work for developers.
Signed-off-by: Marcin Juszkiewicz
W dniu 17.04.2024 o 13:26, Xiong Yining pisze:
Provide functions to check for CPU topology information:
- the number of sockets on sbsa-ref platform.
- the number of clusters in one socket.
- the number of cores in one cluster.
- the number of threads in one cores.
As SMC calls can return up to
W dniu 17.04.2024 o 13:26, Xiong Yining pisze:
To align the CPU topology information recognized by the operating system with
the CPU topology
information configured by QEMU, we need to make use of the CPU topology
information to create
complex PPTT tables setups.
We can get the CPU topology in
W dniu 20.06.2024 o 16:32, Leif Lindholm pisze:
A patch adding a mapping for ImagePropertiesRecordLib introduced a bunch of
LF line endings in otherwise CRLF files, so clean that up.
Cc: Ard Biesheuvel
Cc: Chuong Tran
Cc: Graeme Gregory
Cc: Marcin Juszkiewicz
Cc: Marcin Wojtas
Cc: Meenakshi
W dniu 19.06.2024 o 09:09, Ard Biesheuvel pisze:
On Wed, 19 Jun 2024 at 07:52, Marcin Juszkiewicz
wrote:
QEMU no longer permits misaligned access to device memory, which breaks
QemuVideoDxe on SbsaQemu.
c1d1910be6e04a8b1a73090cf2881fb698947a6e commit in EDK2 fixed it by
enabling WriteCombine
QEMU no longer permits misaligned access to device memory, which breaks
QemuVideoDxe on SbsaQemu.
c1d1910be6e04a8b1a73090cf2881fb698947a6e commit in EDK2 fixed it by
enabling WriteCombine for Framebuffer memory. This change enables that
fix.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu
W dniu 3.06.2024 o 18:47, Leif Lindholm via groups.io pisze:
In 2020 we got version C of spec (and then D, E, F) which allows to
use more registers:
> Allow R4—R7 (SMC32/HVC32) to be used as result registers.
> Allow X8—X17 to be used as parameter registers in SMC64/HVC64.
> Allow X4—X17 to
W dniu 28.05.2024 o 16:31, Ard Biesheuvel pisze:
I would expect each host bridge to have its own separate resource
windows for config space, buses and MMIO regions.
So each host bridge gets a different segment number, and each segment
is associated with a different ECAM region. That also means t
EDK2/ArmPkg/Library/ArmSmcLib has code to do SMC calls.
There are ArmCallSmc[0-3]() functions for up to 3 arguments/results and
ArmCallSmc() function which can use 7 arguments and get 4 results back.
This implementation looks like version B (Nov 2016) of SMCCC
specification [1] with one more
W dniu 29.05.2024 o 15:30, Leif Lindholm via groups.io pisze:
On 2024-05-29 14:29, Marcin Juszkiewicz wrote:
Update TF-A binaries to the same version as QEMU CI uses.
Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Leif Lindholm
Thanks, pushed as 5fdbccd742d4206a2370a08c5420a1aa8c6ad85b
Update TF-A binaries to the same version as QEMU CI uses.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/Sbsa/Readme.md | 49 ---
Platform/Qemu/Sbsa/bl1.bin | Bin 23349 -> 2 bytes
Platform/Qemu/Sbsa/fip.bin | Bin 82722 -> 82722 bytes
3
Update TF-A binaries to the same version as QEMU CI uses.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/Sbsa/bl1.bin | Bin 23349 -> 2 bytes
Platform/Qemu/Sbsa/fip.bin | Bin 82722 -> 82722 bytes
2 files changed, 0 insertions(+), 0 deletions(-)
mode change 100755 => 100644
.txt
I am wondering where I made mistakes in handling PCIe buses.
Thanks go to Leif for pointing me to use of Aml to generate SSDT tables.
Cc: Leif Lindholm
Cc: Ard Biesheuvel
Cc: Graeme Gregory
Cc: Ray Ni
To: devel@edk2.groups.io
Signed-off-by: Marcin Juszkiewicz
---
Changes in v2:
- Dropped [W
We want to have dynaminc PCI Express variables. Which forces us to
generate MCFG from C code.
Signed-off-by: Marcin Juszkiewicz
---
Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 -
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c| 83
Silicon/Qemu/SbsaQemu
We can have more than one PCI Express bus. So instead of having static
description in DSDT we create SSDT table for each existing PCIe bus.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 2 +
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
SbsaQemu assumes that there is only one PCI Express bus. But there can
be multiple PCIe buses as NUMA systems can get 'pxb-pcie' HostBridge
devices added.
Let scan for all PCIe buses and report them back so EDK2 will be able to
find all expansions.
Signed-off-by: Marcin J
W dniu 17.05.2024 o 09:17, Chao Li via groups.io pisze:
This library is copied from ArmVirtPkg, in the Arm version, the value of
PcdFlashNvStorageVariableBase, PcdFlashNvStorageFtwWorkingBase and
PcdFlashNvStorageFtwSpareBase are hardcoded in INC file.
This version will calculate them from FDT r
W dniu 1.05.2024 o 19:43, Michael D Kinney via groups.io pisze:
I would like to propose that TianoCore move all code review from email
based code reviews to GitHub Pull Requests based code reviews.
The proposed date to switch would be immediately after the next stable
tag which is currently sche
We can have more than one PCI Express bus. So instead of having static
description in DSDT we create SSDT table for each existing PCIe bus.
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 2 +
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.inf
We want to have dynaminc PCI Express variables. Which forces us to
generate MCFG from C code.
Signed-off-by: Marcin Juszkiewicz
---
Silicon/Qemu/SbsaQemu/AcpiTables/AcpiTables.inf | 1 -
.../Drivers/SbsaQemuAcpiDxe/SbsaQemuAcpiDxe.c| 83
Silicon/Qemu/SbsaQemu
.txt
I am wondering where I made mistakes in handling PCIe buses.
Thanks go to Leif for pointing me to use of Aml to generate SSDT tables.
Cc: Leif Lindholm
Cc: Ard Biesheuvel
Cc: Graeme Gregory
Cc: Ray Ni
To: devel@edk2.groups.io
Signed-off-by: Marcin Juszkiewicz
---
Marcin Jusz
SbsaQemu assumes that there is only one PCI Express bus. But there can
be multiple PCIe buses as NUMA systems can get 'pxb-pcie' HostBridge
devices added.
Let scan for all PCIe buses and report them back so EDK2 will be able to
find all expansions.
Signed-off-by: Marcin J
FEAT_ECV for QEMU v9.0+ to get access to CNTPOFF register.
Signed-off-by: Marcin Juszkiewicz
Reviewed-by: Leif Lindholm
Thanks!
Can you push the change yourself?
Thanks, pushed.
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View/Reply Online (#118233): https
The more I dig in EDK2 during SbsaQemu work, the more I see duplicated
code.
Want to scan PCI bus to check for host bridges? Two or three
implementations exist. Want to calculate checksum of just created ACPI
table? AcpiPlatformChecksum() has several, incompatible with each other,
implementat
Timer interrupts are set by ArmPkg.dec to recommended values.
We do not need to repeat it (and we missed HypVirtIntrNum one).
Signed-off-by: Marcin Juszkiewicz
---
Platform/Qemu/SbsaQemu/SbsaQemu.dsc | 10 --
1 file changed, 10 deletions(-)
diff --git a/Platform/Qemu/SbsaQemu
() {
Remark 2173 - Creation of named objects within a method is highly
inefficient, use globals or method local variables instead ^
(\_SB.PCI0._CRS)
Simplified some _CRS nodes.
Signed-off-by: Marcin Juszkiewicz
---
Silicon/Qemu/SbsaQemu/AcpiTables/Dsdt.asl | 23 ---
1 file
I am working on some changes to SbsaQemu and got some cleanups in
meantime.
First patch gets rid of setting Pcds for Timer interrupts. ArmPkg does
it for us so we do not have to.
Second changes DSDT nodes so iasl does not complain.
Marcin Juszkiewicz (2):
SbsaQemu: do not set Timer interrupts
-by: Marcin Juszkiewicz
---
Platform/Qemu/Sbsa/Readme.md | 55 ++-
Platform/Qemu/Sbsa/bl1.bin | Bin 23365 -> 23349 bytes
Platform/Qemu/Sbsa/fip.bin | Bin 82722 -> 82722 bytes
3 files changed, 28 insertions(+), 27 deletions(-)
diff --git a/Platform/Qem
IASL complained that DSDT is not optimal:
Dsdt.
83: Name (RBUF, ResourceTemplate() {
Remark 2173 - Creation of named objects within a method is highly
inefficient, use globals or method local variables instead ^
(\_SB.USB0._CRS)
Dsdt.
377: Name (RBUF, ResourceTemplate
W dniu 16.04.2024 o 09:38, Marcin Juszkiewicz via groups.io pisze:
And if someone considers using ConfigurationManager for their platform:
please reconsider it as it may not be worth your time.
Wrote blog post about my adventure with CM:
https://marcin.juszkiewicz.com.pl/2024/04/16
W dniu 12.04.2024 o 14:43, Marcin Juszkiewicz via groups.io pisze:
W dniu 8.10.2023 o 19:25, Marcin Juszkiewicz via groups.io pisze:
I hate replying to myself after half a year of not seeing any answer. So
added some people from repo to Cc:
Can someone point me to documentation on how to use
W dniu 8.10.2023 o 19:25, Marcin Juszkiewicz via groups.io pisze:
I hate replying to myself after half a year of not seeing any answer. So
added some people from repo to Cc:
Can someone point me to documentation on how to use ACPI table
generators and ConfigurationManagerProtocol?
https
W dniu 28.03.2024 o 07:19, Xiong Yining pisze:
Add support to create SRAT(System resource affinity table) for
sbsa platform at runtime.
Signed-off-by: Xiong Yining
Reviewed-by: Marcin Juszkiewicz
Reviewed-by: Leif Lindholm
When you send a new version of patch, with changes done compared to
W dniu 20.02.2024 o 08:47, Xiong Yining pisze:
Add support to create SRAT(System resource affinity table) for
sbsa platform at runtime.
Signed-off-by: Xiong Yining
Signed-off-by: Chen Baozi
Needs rebase on top of "get rid of DeviceTree from SbsaQemu" series.
Rename SbsaQemuHardwareInfoLib to
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