;
> Attach sample code snippet and data dump from my side.
>
> Thanks,
> Ian Chiu
>
>
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Sean Rhodes
> Sent: Monday, December 5, 2022 5:18 PM
> To: devel@edk2.groups.io
> Cc: Matt DeVillier ; Wu, Hao A &
From: Matt DeVillier
On some platforms, including Sky Lake and Kaby Lake, the PSIV (Protocol
Speed ID Value) indices are shared between Protocol Speed ID DWORD' in
the extended capabilities registers for both USB2 (Full Speed) and USB3
(Super Speed).
An example can be found below:
XhcCheckU
vel@edk2.groups.io<mailto:devel@edk2.groups.io>
> Cc: Matt DeVillier
> mailto:matt.devill...@gmail.com>>; Wu, Hao A
> mailto:hao.a...@intel.com>>; Ni, Ray
> mailto:ray...@intel.com>>; Rhodes, Sean
> mailto:sean@starlabs.systems>>
> Subject: [e
; Best Regards,
> Hao Wu
>
> > -Original Message-
> > From: devel@edk2.groups.io On Behalf Of Sean
> > Rhodes
> > Sent: Friday, December 2, 2022 4:25 AM
> > To: devel@edk2.groups.io
> > Cc: Matt DeVillier ; Wu, Hao A
> > ; Ni, Ray ; Rhodes, Sean
> &g
er 2, 2022 4:25 AM
> To: devel@edk2.groups.io
> Cc: Matt DeVillier ; Wu, Hao A
> ; Ni, Ray ; Rhodes, Sean
>
> Subject: [edk2-devel] [PATCH 1/4] MdeModulePkg/XhciDxe/XhciReg: Handle
> incorrect PSIV indices
>
> From: Matt DeVillier
>
> On some platforms, including
From: Matt DeVillier
On some platforms, including Sky Lake and Kaby Lake, the PSIV (Protocol
Speed ID Value) indicesare shared between Protocol Speed ID DWORD' in
the extended capabilities registers for both USB2 (Full Speed) and USB3
(Super Speed).
An example can be found below:
XhcCheckUs
