>
> Reviewed-by: Michael D Kinney
>
> Mike
>
> > -Original Message-
> > From: Javeed, Ashraf
> > Sent: Thursday, July 23, 2020 4:58 AM
> > To: Gao, Liming ; devel@edk2.groups.io
> > Cc: Kinney, Michael D
> > Subject: RE: [edk2-dev
0 4:58 AM
> To: Gao, Liming ;
> devel@edk2.groups.io
> Cc: Kinney, Michael D
> Subject: RE: [edk2-devel] [PATCH V3 1/2]
> MdePkg/Include/IndustryStandard: CXL 1.1 Registers
>
> Liming;
> My response inline.
>
> Thanks for the review.
> Ashraf
>
> &g
e/IndustryStandard:
> CXL 1.1 Registers
>
> Ashraf:
>
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Javeed,
> Ashraf
> Sent: 2020年7月22日 23:22
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D ; Gao, Liming
>
> Subject: [edk2-devel] [
Ashraf:
-Original Message-
From: devel@edk2.groups.io On Behalf Of Javeed, Ashraf
Sent: 2020年7月22日 23:22
To: devel@edk2.groups.io
Cc: Kinney, Michael D ; Gao, Liming
Subject: [edk2-devel] [PATCH V3 1/2] MdePkg/Include/IndustryStandard: CXL 1.1
Registers
BZ: https
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611
Register definitions from chapter 7 of Compute Express Link
Specification Revision 1.1 are ported into the new Cxl11.h.
The CXL Flex Bus registers are based on the PCIe Extended Capability
DVSEC structure header, led to the inclusion of
