REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4478
This series adds support for building RiscVVirtQemu EDK2 using
CLANGDWARF toolchain. Adding this support helps people to use
the same toolchain to build EDK2 for different architectures.
Cc: Rebecca Cran <rebe...@bsdio.com>
Cc: Liming Gao <gaolim...@byosoft.com.cn>
Cc: Bob Feng <bob.c.f...@intel.com>
Cc: Yuwei Chen <yuwei.c...@intel.com>
Cc: Ard Biesheuvel <ardb+tianoc...@kernel.org>
Cc: Jiewen Yao <jiewen....@intel.com>
Cc: Jordan Justen <jordan.l.jus...@intel.com>
Cc Gerd Hoffmann <kra...@redhat.com>
Cc: Andrei Warkentin <andrei.warken...@intel.com>
Cc: Heinrich Schuchardt <heinrich.schucha...@canonical.com>
Changes since v1:
1) Addressed Liming's comments in PATCH 3.
Sunil V L (4):
OvmfPkg/RiscVVirt: use 'auto' alignment and FIXED for XIP modules
OvmfPkg/RiscVVirt: SecEntry: Remove unnecessary assembly directives
BaseTools/tools_def: Add CLANGDWARF support for RISC-V
OvmfPkg/RiscVVirt: Update README for CLANGDWARF support
OvmfPkg/RiscVVirt/RiscVVirtQemu.fdf | 34 ++++++------------
BaseTools/Conf/tools_def.template | 53 +++++++++++++++++++++++++++++
OvmfPkg/RiscVVirt/README.md | 28 +++++++++++++--
OvmfPkg/RiscVVirt/Sec/SecEntry.S | 3 --
4 files changed, 88 insertions(+), 30 deletions(-)
--
2.34.1
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