From: Tom Lendacky <thomas.lenda...@amd.com> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2198
Under SEV-ES, a CPUID intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Add support to construct the required GHCB values to support a CPUID NAE event. Additionally, CPUID 0x0000_000d requires XCR0 to be supplied in the GHCB, so add support to issue the XGETBV instruction. Cc: Eric Dong <eric.d...@intel.com> Cc: Ray Ni <ray...@intel.com> Cc: Laszlo Ersek <ler...@redhat.com> Signed-off-by: Tom Lendacky <thomas.lenda...@amd.com> --- .../X64/AMDSevVcCommon.c | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c index ce5514fd0fb6..29119ba863d3 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/AMDSevVcCommon.c @@ -4,6 +4,8 @@ #include <Library/DebugLib.h> #include "AMDSevVcCommon.h" +#define CR4_OSXSAVE (1 << 18) + typedef enum { LongMode64Bit = 0, LongModeCompat32Bit, @@ -481,6 +483,45 @@ IoioExit ( return 0; } +STATIC +UINTN +CpuidExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINTN Status; + + Ghcb->SaveArea.Rax = Regs->Rax; + GhcbSetRegValid (Ghcb, GhcbRax); + Ghcb->SaveArea.Rcx = Regs->Rcx; + GhcbSetRegValid (Ghcb, GhcbRcx); + if (Regs->Rax == 0x0000000d) { + Ghcb->SaveArea.XCr0 = (AsmReadCr4 () & CR4_OSXSAVE) ? AsmXGetBv (0) : 1; + GhcbSetRegValid (Ghcb, GhcbXCr0); + } + + Status = VmgExit (Ghcb, SvmExitCpuid, 0, 0); + if (Status) { + return Status; + } + + if (!GhcbIsRegValid (Ghcb, GhcbRax) || + !GhcbIsRegValid (Ghcb, GhcbRbx) || + !GhcbIsRegValid (Ghcb, GhcbRcx) || + !GhcbIsRegValid (Ghcb, GhcbRdx)) { + VmgExit (Ghcb, SvmExitUnsupported, SvmExitCpuid, 0); + ASSERT (0); + } + Regs->Rax = Ghcb->SaveArea.Rax; + Regs->Rbx = Ghcb->SaveArea.Rbx; + Regs->Rcx = Ghcb->SaveArea.Rcx; + Regs->Rdx = Ghcb->SaveArea.Rdx; + + return 0; +} + UINTN DoVcCommon ( GHCB *Ghcb, @@ -497,6 +538,10 @@ DoVcCommon ( ExitCode = Regs->ExceptionData; switch (ExitCode) { + case SvmExitCpuid: + NaeExit = CpuidExit; + break; + case SvmExitIoioProt: NaeExit = IoioExit; break; -- 2.17.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47656): https://edk2.groups.io/g/devel/message/47656 Mute This Topic: https://groups.io/mt/34203559/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-