.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Sean via
Groups.Io
Sent: Sunday, March 8, 2020 6:09 AM
To: Chang, Abner (HPS SW/FW Technologist) ;
devel@edk2.groups.io
Subject: Re: [edk2-devel] [edk2/master PATCH RISC-V CI v1 6/6] .pytool: Add
RISC-V architecture on RISC-V EDK2 CI.
I never
I never saw a patch in the series that actually added the submodule to the
.gitmodules file but maybe i missed that. If that is approved then the changes
to this file look ok. I have no idea why all the line endings are shown but
the substantial changes here look fine to me.
BZ:2562:
https://bugzilla.tianocore.org/show_bug.cgi?id=2562
Add RISC-V architecture on RISC-V EDK2 CI testing.
Signed-off-by: Abner Chang
Cc: Bret Barkelew
Cc: Sean Brogan
Cc: Leif Lindholm
Cc: Michael D Kinney
Cc: Gilbert Chen
Cc: Daniel Helmut Schaefer
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.pytool/CISettings.py | 15
