REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2322
The current set of maintainers do not plan to maintain this package
moving forward. Simply leaving the code as unmaintained is
undesirable for several reasons including presence of build issues,
functional issues, and lack of consistency with other Intel
platform/silicon code in design and usage.
It is suggested that these be removed for the next stable tag due
to lack of recent testing.
This change removes all remaining .asi files used by the module
BoardAcpiDxe in PurleyOpenBoardPkg.
Cc: Nate DeSimone <nathaniel.l.desim...@intel.com>
Cc: Michael D Kinney <michael.d.kin...@intel.com>
Cc: Shifei A Lu <shifei.a...@intel.com>
Cc: Isaac W Oram <isaac.w.o...@intel.com>
Cc: Xiaohu Zhou <bowen.z...@intel.com>
Signed-off-by: Michael Kubacki <michael.a.kuba...@intel.com>
---
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CommonPlatform.asi |
227 ------
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Mother.asi |
202 -----
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Os.asi |
145 ----
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pch.asi |
10 -
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchApic.asi |
17 -
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci1.asi |
91 ---
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci2.asi |
92 ---
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchLpc.asi |
22 -
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchSata.asi |
807 --------------------
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchXhci.asi |
329 --------
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciCrs.asi |
312 --------
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciIrq.asi |
455 -----------
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHp.asi |
644 ----------------
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHpDev.asi |
14 -
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieNonHpDev.asi |
16 -
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieSeg.asi |
355 ---------
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi |
78 --
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck1Ejd.asi |
9 -
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck2Ejd.asi |
9 -
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck3Ejd.asi |
9 -
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore0.asi |
33 -
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore1.asi |
175 -----
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore2.asi |
125 ---
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore3.asi |
98 ---
24 files changed, 4274 deletions(-)
diff --git
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CommonPlatform.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CommonPlatform.asi
deleted file mode 100644
index f5317cff86..0000000000
---
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/CommonPlatform.asi
+++ /dev/null
@@ -1,227 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include "MaxSocket.h"
-
- //
- // External declarations
- // HECI-1/HECI-2 are in PurleyPlatPkg\Me\Sps\Acpi\SpsNm.asl
- //
- External(\_SB.PC00.HEC2.HPTS, MethodObj)
- External(\_SB.PC00.HEC2.HWAK, MethodObj)
-
- //
- // System Sleep States
- //
- Name (\_S0,Package (){0,0,0,0})
- Name (\_S3,Package (){5,0,0,0}) // Name changed to \DS3 if disabled in
Setup
- Name (\_S4,Package (){6,0,0,0}) // Name changed to \DS4 if disabled in
Setup
- Name (\_S5,Package (){7,0,0,0})
-
- //
- // Native OS hot plug support, 0->ACPI, 1->OS
- //
- Name (\OSHF, 0)
-
- //
- // OS flag
- //
- #include "Os.asi"
-
- //
- // for determing PIC mode
- //
- Name (\PICM,Zero)
- Method (\_PIC, 1, NotSerialized) {
- Store(Arg0,\PICM)
- }
-
- OperationRegion (DBG0, SystemIO, 0x80, 2)
- Field (DBG0, ByteAcc,NoLock,Preserve) {
- IO80, 8,
- IO81, 8
- }
-
- //
- // Access CMOS range
- //
- OperationRegion (ACMS, SystemIO, 0x72, 2)
- Field ( ACMS, ByteAcc, NoLock, Preserve) {
- INDX, 8,
- DATA, 8
- }
-
- //
- // SWGPE_CTRL
- //
- OperationRegion (GPCT, SystemIO, 0x442, 1)
- Field ( GPCT, ByteAcc, NoLock, Preserve) {
- , 1,
- SGPC , 1,
- }
-
- //
- // GPI_INV
- //
- OperationRegion (GPIV, SystemIO, 0x52c, 2)
- Field ( GPIV, ByteAcc, NoLock, Preserve) {
- GP0I , 1,
- }
-
-#include "Acpi/GlobalNvs.asi"
-
- //
- // Operation region for GPI status bits
- //
- OperationRegion (GSTS, SystemIO, 0x422, 2)
- Field ( GSTS, ByteAcc, NoLock, Preserve) {
- GP00 , 1,
- , 12,
- GP13 , 1,
- }
-
- //
- // GPE0 HOT_PLUG_EN
- //
- OperationRegion (GPE0, SystemIO, 0x428, 8)
- Field (GPE0, ByteAcc,NoLock,Preserve) {
- ,1,
- GPEH,1,
- ,1,
- USB1,1,
- USB2,1,
- USB5,1,
- ,3,
- PCIE,1,
- ,1,
- PMEE,1,
- USB3,1,
- PMB0,1,
- USB4,1,
- ,9,
- ,1,
- ,7,
- USB6,1,
- ,15,
- }
-
- //
- // GPES Status
- //
- OperationRegion (GPES, SystemIO, 0x420, 8)
- Field (GPES, ByteAcc,NoLock,Preserve) {
- ,1,
- GPSH,1,
- SGPS,1,
- US1S,1,
- US2S,1,
- US5S,1,
- ,1,
- SMWS,1,
- ,1,
- PEES,1,
- ,1,
- PMES,1,
-
- US3S ,1,
- PMBS,1,
- US4S ,1,
- ,9,
- ,1,
- ,7,
- US6S,1,
- ,15,
- }
-
- //
- // System sleep down
- //
- Method (_PTS, 1, NotSerialized)
- {
- Store (0x72, IO80) // Sync with EfiPostCode.h
-
- //
- // Clear wake event status.
- //
- Store(1,US1S)
- Store(1,US2S)
- Store(1,US5S)
- Store(1,SMWS)
- Store(1,PMES)
- Store(1,US3S)
- Store(1,PMBS)
- Store(1,US4S)
- Store(1,US6S)
-
- //
- // Enable SCI and wake event sources.
- //
- Store(1,GPEH)
- Store(1,USB1)
- Store(1,USB2)
- Store(1,USB5)
- Store(1,PCIE)
- Store(1,PMEE)
- Store(1,USB3)
- Store(1,PMB0)
- Store(1,USB4)
- Store(1,USB6)
-
- //
- // If HECI-2 exist call its prepare-to-sleep handler.
- // The handler checks whether HECI-2 is enabled.
- //
- If (CondRefOf(\_SB.PC00.HEC2.HPTS))
- {
- \_SB.PC00.HEC2.HPTS()
- }
-
- /// WA for S3 on XHCI
- \_SB.PC00.XHCI.XHCS()
- }
-
- //#include "Uncore.asi"
-
- //
- // System Wake up
- //
- Method (_WAK, 1, Serialized)
- {
- Store (0x73, IO80) // Sync with EfiPostCode.h
-
- //
- // If HECI-2 exist call its wake-up handler.
- // The handler checks whether HECI-2 is enabled.
- //
- If (CondRefOf(\_SB.PC00.HEC2.HWAK))
- {
- \_SB.PC00.HEC2.HWAK()
- }
-
- //
- // If waking from S3
- //
- If (LEqual(Arg0, 3)) {
- }
-
- Return(Package(){0, 0})
- }
-
- Scope(\_SB) {
-
- // Information on CPU and Memory for hotplug SKUs
- // #include "CpuMemHp.asi"
-
- OperationRegion (IOB2, SystemIO, 0xB2, 2) //MKF_SMIPORT
- Field (IOB2, ByteAcc, NoLock, Preserve) {
- SMIC, 8, // SW-SMI ctrl port
- SMIS, 8, // SW-SMI status port
- }
-
- } // end _SB scope
-
-
diff --git
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Mother.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Mother.asi
deleted file mode 100644
index 863518b3a5..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Mother.asi
+++ /dev/null
@@ -1,202 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-Device (DMAC) {
- Name (_HID, EISAID("PNP0200"))
- Name (_CRS,ResourceTemplate() {
- IO(Decode16, 0x0, 0x0, 0, 0x10)
- IO(Decode16, 0x81, 0x81, 0, 0x3)
- IO(Decode16, 0x87, 0x87, 0, 0x1)
- IO(Decode16, 0x89, 0x89, 0, 0x3)
- IO(Decode16, 0x8f, 0x8f, 0, 0x1)
- IO(Decode16, 0xc0, 0xc0, 0, 0x20)
- DMA(Compatibility,NotBusMaster,Transfer8) {4}
- })
-}
-
-Device (RTC) {
- Name (_HID,EISAID("PNP0B00"))
- Name (_CRS,ResourceTemplate() {
- IO(Decode16,0x70,0x70,0x01,0x02)
- IO(Decode16,0x74,0x74,0x01,0x04)
- IRQNoFlags(){8}
- })
-}
-
-Device (PIC) {
- Name (_HID,EISAID("PNP0000"))
- Name (_CRS,ResourceTemplate() {
- IO(Decode16,0x20,0x20,0x01,0x1E) // length of 1Eh includes all
aliases
- IO(Decode16,0xA0,0xA0,0x01,0x1E)
- IO(Decode16,0x4D0,0x4D0,0x01,0x02)
- })
-}
-
-Device (FPU) {
- Name (_HID,EISAID("PNP0C04"))
- Name (_CRS,ResourceTemplate() {
- IO(Decode16,0xF0,0xF0,0x01,0x1)
- IRQNoFlags(){13}
- })
-}
-
-Device(TMR)
-{
- Name(_HID,EISAID("PNP0100"))
-
- Name(_CRS,ResourceTemplate() {
- IO(Decode16,0x40,0x40,0x01,0x04)
- IO(Decode16,0x50,0x50,0x01,0x04) // alias
- IRQNoFlags(){0}
- })
-}
-
-Device (SPKR) {
- Name (_HID,EISAID("PNP0800"))
- Name (_CRS,ResourceTemplate() {
- IO(Decode16,0x61,0x61,0x01,0x01)
- })
-}
-
-//
-// all "PNP0C02" devices- pieces that don't fit anywhere else
-//
-Device(XTRA) {
- Name(_HID,EISAID("PNP0C02")) // Generic motherboard devices
- Name(_CRS,
- ResourceTemplate() {
- IO(Decode16,0x500,0x500,0x01,0x40) // GPIO space, ICH5
- IO(Decode16,0x400,0x400,0x01,0x80) // PM IO, ICH5
- IO(Decode16,0x92,0x92,0x01,0x01) // INIT & Fast A20
port, ICH5
- //
- // Resource conflict with COM Port
- //
- //IO(Decode16,0x680,0x680,0x01,0x80) // Runtime
registers, National SIO
- IO(Decode16,0x10,0x10,0x01,0x10)
- IO(Decode16,0x72,0x72,0x01,0x02)
- IO(Decode16,0x80,0x80,0x01,0x01)
- IO(Decode16,0x84,0x84,0x01,0x03)
- IO(Decode16,0x88,0x88,0x01,0x01)
- IO(Decode16,0x8c,0x8c,0x01,0x03)
- IO(Decode16,0x90,0x90,0x01,0x10)
- //
- // SMBus decode range
- //
- IO(Decode16,0x540,0x540,0x01,0x40)
- //
- // Pilot Mail Box decode range
- //
- IO(Decode16,0x600,0x600,0x01,0x20)
- //
- // BMC KCS decode range
- //
- IO(Decode16,0xCA0,0xCA0,0x01,0x6)
- //
- // Performance Status and control ports decode range
- //
- IO(Decode16,0x880,0x880,0x01,0x4)
-
- //IO Descriptor added for range 800-81f for S501302
- IO(Decode16,0x800,0x800,0x01,0x20)
- //IO Descriptor added for range 2F8-2FF for S501706
- //IO(Decode16,0x2F8,0x2F8,0x01,0x08)
- //IO(Decode16,0x60,0x60,0x01,0x01)
- //IO(Decode16,0x64,0x64,0x01,0x01)
-
- //PCH_ACPI_FLAG: RCBA is not supported in SPT
- //
- // RCBA memory range
- //
- //Memory32Fixed (ReadOnly, 0xFED1C000, 0x6FFFF) // ICH9 bios spec
section 5.10 - reserved memory address space.
- Memory32Fixed (ReadOnly, 0xFED1C000, 0x24000) // ICH9 bios spec section
5.10 - reserved memory address space.
- // Leave FED40000-FED45000 for TPM
- Memory32Fixed (ReadOnly, 0xFED45000, 0x47000) // ICH9 bios spec section
5.10 - reserved memory address space.
-
- //
- // FLASH range
- //
- Memory32Fixed (ReadOnly, 0xFF000000, 0x1000000) //16MB as per IIO spec
-
- //
- // Local APIC range(0xFEE0_0000 to 0xFEEF_FFFF)
- //
- Memory32Fixed (ReadOnly, 0xFEE00000, 0x100000)
-
- //
- // HECI range, 32 bytes from HECI1_BASE_ADDRESS (0xFE90_0000 to
0xFE90_001F)
- //
- //Memory32Fixed (ReadWrite, 0xFE900000, 0x20)
- Memory32Fixed (ReadWrite, 0xFED12000, 0x10)
-
- //
- // HECI range, 32 bytes from HECI2_BASE_ADDRESS (0xFEA0_0000 to
0xFEA0_001F)
- //
- //Memory32Fixed (ReadWrite, 0xFEA00000, 0x20)
- Memory32Fixed (ReadWrite, 0xFED12010, 0x10)
-
- //
- // IIO RCBA memory range
- //
- Memory32Fixed (ReadOnly, 0xFED1B000, 0x1000)
- }
- )
-}
-
-//
-// High Performance Event Timer (HPET)
-//
-Device (HPET) {
- Name (_HID, EisaId ("PNP0103"))
-
- Method (_STA, 0, NotSerialized) {
- If (\HPTE) {
- Return (0x0F)
- } Else {
- Return (0x00)
- }
- }
-
- Name (CRS0, ResourceTemplate () {
- Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
- })
-
- Name (CRS1, ResourceTemplate () {
- Memory32Fixed (ReadWrite, 0xFED01000, 0x00000400)
- })
-
- Name (CRS2, ResourceTemplate () {
- Memory32Fixed (ReadWrite, 0xFED02000, 0x00000400)
- })
-
- Name (CRS3, ResourceTemplate () {
- Memory32Fixed (ReadWrite, 0xFED03000, 0x00000400)
- })
-
- //
- // Owning control method can't be re-entrant, so _CRS must be Serialized
- //
- Method (_CRS, 0, Serialized) {
- Switch (ToInteger(\HPTB)) {
- Case (0xFED00000) {
- Return (CRS0)
- }
-
- Case (0xFED01000) {
- Return (CRS1)
- }
-
- Case (0xFED02000) {
- Return (CRS2)
- }
-
- Case (0xFED03000) {
- Return (CRS3)
- }
- }
- Return (CRS0)
- }
-}
\ No newline at end of file
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Os.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Os.asi
deleted file mode 100644
index 532e5ba448..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Os.asi
+++ /dev/null
@@ -1,145 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-Scope (\_SB) {
-
- Name (XCNT, 0)
- Name (OSYS, 0) // Global variable for type of OS.
-
- //
- // Device specific method
- //
- Method (_DSM, 4, Serialized) {
- If (LEqual(Arg0,ToUUID("663E35AF-CC10-41A4-88EA-5470AF055295"))){
-
- // L1 DIR POINTER
- Switch (ToInteger(Arg2)) {
- //
- //Function 0: Return supported functions, based on revision
- //
- Case(0)
- {
- Switch (ToInteger(Arg1)) {
- Case(0) {
- If (Lequal(EMCA,1))
- {
- Return ( Buffer() {0x3} )
- }
- Else
- {
- Return (Buffer() {0})
- }
- }
- }
-
- }
- //
- // Function 1:
- //
- Case(1) {Return (LDIR) }
- Default { }
- }
- }
-
- Return (Buffer() {0})
- }
-
- Method (_INI) {
-
- If (CondRefOf (_OSI)) {
-
- If (\_OSI ("Windows 2001.1 SP1")) {
- Store (5, OSYS) // Windows Server 2003 SP1
- }
-
- If (\_OSI ("Windows 2001.1")) {
- Store (6, OSYS) // Windows Server 2003
- }
-
- If (\_OSI ("Windows 2001 SP2")) {
- Store (7, OSYS) // Windows XP SP2
- }
-
- If (\_OSI ("Windows 2001")) {
- Store (8, OSYS) // Windows XP
- }
-
- If (\_OSI ("Windows 2006.1")) {
- Store (9, OSYS) // Windows Server 2008
- }
-
- If (\_OSI ("Windows 2006 SP1")) {
- Store (10, OSYS) // Windows Vista SP1
- }
-
- If (\_OSI ("Windows 2006")) {
- Store (11, OSYS) // Windows Vista
- }
-
- If (\_OSI ("Windows 2009")) {
- Store (12, OSYS) // Windows Server 2008 R2 & Windows 7
- }
-
- If (\_OSI ("Windows 2012")) {
- Store (13, OSYS) // Windows Server 2012 & Windows 8
- }
-
- If (\_OSI ("Windows 2013")) {
- Store (14, OSYS) // Windows Server 2012 R2 & Windows 8.1
- }
-
- If (\_OSI ("Windows 2015")) {
- Store (15, OSYS) // Windows 10 & Windows Server Technical Preview
- }
-
- If (\_OSI ("Windows 2016")) {
- Store (16, OSYS) // Windows 10, version 1607
- }
-
- If (\_OSI ("Windows 2017")) {
- Store (17, OSYS) // Windows 10, version 1703
- }
-
- //
- // Check Linux also
- //
- If (\_OSI ("Linux")) {
- Store (1, OSYS)
- }
-
- If (\_OSI ("FreeBSD")) {
- Store (2, OSYS)
- }
-
- If (\_OSI ("HP-UX")) {
- Store (3, OSYS)
- }
-
- If (\_OSI ("OpenVMS")) {
- Store (4, OSYS)
- }
-
- //
- // Running WinSvr2012, Win8, or later?
- //
- If (LGreaterEqual (\_SB.OSYS, 13)) {
- //
- // It is Svr2012 or Win8
- // Call xHCI device to switch USB ports over
- // unless it has been done already
- //
- If (LEqual (XCNT, 0)) {
- Store (0x84, IO80)
- Increment (XCNT)
- }
- } Else {
- Store (\_SB.OSYS, IO80)
- }
- }
- } // End Method (_INI)
-
-} // End Scope (_SB)
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pch.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pch.asi
deleted file mode 100644
index 6b9ae9b3e7..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Pch.asi
+++ /dev/null
@@ -1,10 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-//
-// I/O controller miscellaneous
-//
diff --git
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchApic.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchApic.asi
deleted file mode 100644
index 57bc9f2ba1..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchApic.asi
+++ /dev/null
@@ -1,17 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-Device(APIC) {
- Name (_HID,EISAID("PNP0003")) // APIC resources
- Name (_CRS, ResourceTemplate() {
- //
- // APIC range(0xFEC0_0000 to 0xFECF_FFFF)
- //
- Memory32Fixed (ReadOnly, 0xFEC00000, 0x100000) // IO APIC
- }
- )
-}
diff --git
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci1.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci1.asi
deleted file mode 100644
index c25af50ed8..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci1.asi
+++ /dev/null
@@ -1,91 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-Name (OPAC, 0)
-
-OperationRegion(PWKE,PCI_Config,0x54,0x18)
-Field(PWKE,DWordAcc,NoLock,Preserve)
-{
- , 8,
- PMEE, 1, // PWR_CNTL_STS.PME_En
- , 6,
- PMES, 1, // PWR_CNTL_STS.PME_Sts
- Offset (0x0E),
- , 1,
- PWUC, 10 // Port Wake Up Capability Mask
-}
-
-//
-// Indicate access to OperationRegions is enabled/disabled
-//
-Method (_REG, 2)
-{
- // If OperationRegion ID = PCI_Config
- //
- If (LEqual (Arg0, 2))
- {
- // If access is enabled
- //
- If (LEqual(Arg1, 1))
- {
- // Set local flag
- //
- Store (One, OPAC)
- }
- Else
- {
- // Clear local flag
- //
- Store (One, OPAC)
- }
- }
-}
-
-//
-// Enable/disable ports on this controller to wake the system
-//
-Method (_PSW,1)
-{
- If (Arg0)
- {
- Store (Ones,PWUC)
- }
- Else
- {
- Store (0,PWUC)
- }
-}
-
-//
-// Initialization for this controller
-//
-Method (_INI, 0)
-{
- // If access to OperationRegion is enabled
- //
- If (LEqual (OPAC, One))
- {
- Store (1, PMES) // clear PME status
- Store (0, PMEE) // clear PME enable
- }
-}
-
-// The CRB leaves the USB ports on in S3/S4 to allow
-// the ability to Wake from USB. Therefore, define
-// the below control methods to state D2 entry during
-// the given S-State.
-
-Method(_S3D,0)
-{
- Return(2)
-}
-
-Method(_S4D,0)
-{
- Return(2)
-}
-
diff --git
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci2.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci2.asi
deleted file mode 100644
index 8caae9bbac..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchEhci2.asi
+++ /dev/null
@@ -1,92 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-Name (OPAC, 0)
-
-OperationRegion(PWKE,PCI_Config,0x54,0x18)
-Field(PWKE,DWordAcc,NoLock,Preserve)
-{
- , 8,
- PMEE, 1, // PWR_CNTL_STS.PME_En
- , 6,
- PMES, 1, // PWR_CNTL_STS.PME_Sts
- Offset (0x0E),
- , 1,
- PWUC, 10 // Port Wake Up Capability Mask
-}
-
-//
-// Indicate access to OperationRegions is enabled/disabled
-//
-Method (_REG, 2)
-{
- // If OperationRegion ID = PCI_Config
- //
- If (LEqual (Arg0, 2))
- {
- // If access is enabled
- //
- If (LEqual(Arg1, 1))
- {
- // Set local flag
- //
- Store (One, OPAC)
- }
- Else
- {
- // Clear local flag
- //
- Store (One, OPAC)
- }
- }
-}
-
-//
-// Enable/disable ports on this controller to wake the system
-//
-Method (_PSW,1)
-{
- If (Arg0)
- {
- Store (Ones,PWUC)
- }
- Else
- {
- Store (0,PWUC)
- }
-}
-
-//
-// Initialization for this controller
-//
-Method (_INI, 0)
-{
- // If access to OperationRegion is enabled
- //
- If (LEqual (OPAC, One))
- {
- Store (1, PMES) // clear PME status
- Store (0, PMEE) // clear PME enable
- }
-}
-
-// The CRB leaves the USB ports on in S3/S4 to allow
-// the ability to Wake from USB. Therefore, define
-// the below control methods to state D2 entry during
-// the given S-State.
-
-Method(_S3D,0)
-{
- Return(2)
-}
-
-Method(_S4D,0)
-{
- Return(2)
-}
-
-
diff --git
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchLpc.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchLpc.asi
deleted file mode 100644
index d62d5044b4..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchLpc.asi
+++ /dev/null
@@ -1,22 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-//
-// Define bits in LPC bridge config space
-// (\_SB.PCI0.LPC0)
-//
-OperationRegion (LPCB, PCI_Config, 0x00, 0x100)
-Field (LPCB, DWordAcc, NoLock, Preserve)
-{
- Offset (0xAC),
- , 16,
- XSMB, 1 // set when OS routes USB ports
to xHCI in SmartAuto mode so next POST will know
-}
-
-#include "IrqLink.asl" // PCI routing control methods
-#include "Mother.asi" // Static motherboard device resource declaration
-
diff --git
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchSata.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchSata.asi
deleted file mode 100644
index a74c9b9aae..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchSata.asi
+++ /dev/null
@@ -1,807 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
- OperationRegion (IDER,PCI_Config,0x40,0x20)
- Field (IDER, AnyAcc, NoLock, Preserve)
- {
- PFT0 , 1 , // Drive 0 Fast Timing Bank (TIME0)
- PIE0 , 1 , // Drive 0 IORDY Sample Point Enable (IE0)
- PPE0 , 1 , // Drive 0 Prefetch/Posting Enable (PPE0)
- PDE0 , 1 , // Drive 0 DMA Timing Enable (DTE0)
- PFT1 , 1 , // Drive 1 Fast Timing Bank (TIME1)
- PIE1 , 1 , // Drive 1 IORDY Sample Point Enable (IE1)
- PPE1 , 1 , // Drive 1 Prefetch/Posting Enable (PPE1)
- PDE1 , 1 , // Drive 1 DMA Timing Enable (DTE1)
- PRT0 , 2 , // Drive 0 Recovery Time (RCT)
- , 2 , // Reserved
- PIP0 , 2 , // Drive 0 IORDY Sample Point (ISP)
- PSIT , 1 , // Drive 1 Timing Register Enable (SITRE)
- PIDE , 1 , // IDE Decode Enable (IDE)
- offset (0x2) ,
- SFT0 , 1 , // Drive 0 Fast Timing Bank (TIME0)
- SIE0 , 1 , // Drive 0 IORDY Sample Point Enable (IE0)
- SPE0 , 1 , // Drive 0 Prefetch/Posting Enable (PPE0)
- SDE0 , 1 , // Drive 0 DMA Timing Enable (DTE0)
- SFT1 , 1 , // Drive 1 Fast Timing Bank (TIME1)
- SIE1 , 1 , // Drive 1 IORDY Sample Point Enable (IE1)
- SPE1 , 1 , // Drive 1 Prefetch/Posting Enable (PPE1)
- SDE1 , 1 , // Drive 1 DMA Timing Enable (DTE1)
- SRT0 , 2 , // Drive 0 Recovery Time (RCT)
- , 2 , // Reserved
- SIP0 , 2 , // Drive 0 IORDY Sample Point (ISP)
- SSIT , 1 , // Drive 1 Timing Register Enable (SITRE)
- SIDE , 1 , // IDE Decode Enable (IDE)
-
- PRT1 , 2 , // Drive 1 Recovery Time (RCT)
- PIP1 , 2 , // Drive 1 IORDY Sample Point (ISP)
- SRT1 , 2 , // Drive 1 Recovery Time (RCT)
- SIP1 , 2 , // Drive 1 IORDY Sample Point (ISP)
-
- offset (0x08) ,
-
- UDM0 , 1 , // Primary Drive 0 Synchronous DMA Mode Enable
- UDM1 , 1 , // Primary Drive 1 Synchronous DMA Mode Enable
- UDM2 , 1 , // Secondary Drive 0 Synchronous DMA Mode Enable
- UDM3 , 1 , // Secondary Drive 1 Synchronous DMA Mode Enable
-
- offset (0x0A) ,
-
- PCT0 , 2 , // Primary Drive 0 Cycle Time (PCT0)
- , 2 , // Reserved
- PCT1 , 2 , // Primary Drive 1 Cycle Time (PCT1)
- , 2 , // Reserved
- SCT0 , 2 , // Secondary Drive 0 Cycle Time (SCT0)
- , 2 , // Reserved
- SCT1 , 2 , // Secondary Drive 1 Cycle Time (SCT1)
-
- offset (0x14) ,
- PCB0 , 1 , // Primary Drive 0 Base Clock (PCB0)
- PCB1 , 1 , // Primary Drive 0 Base Clock (PCB0)
- SCB0 , 1 , // Secondary Drive 1 Base Clock (SCB0)
- SCB1 , 1 , // Secondary Drive 1 Base Clock (SCB1)
- PCCR , 2 , // Primary Channel Cable Reporting
- SCCR , 2 , // Secondary Channel Cable Reporting
- , 4 , // Reserved
- PUM0 , 1 , // Primary Drive 0 UDMA 5 Supported
- PUM1 , 1 , // Primary Drive 1 UDMA 5 Supported
- SUM0 , 1 , // Secondary Drive 0 UDMA 5 Supported
- SUM1 , 1 , // Secondary Drive 1 UDMA 5 Supported
- PSIG , 2 , // PRIM_SIG_MODE
- SSIG , 2 , // SEC_SIG_MODE
- }
-
- //
- // Get PIO Timing
- // Arg0 Fast PIO Timing
- // Arg1 DMA Fast Timing
- // Arg2 RCT Timing
- // Arg3 ISP Timing
- //
-
- Method(GPIO,4)
- {
-
- If (LEqual (Or (Arg0, Arg1) , 0) ) {
- //
- // No PIO Timing and DMA Timing support
- //
- Return (0xFFFFFFFF)
-
- } Else {
- If (And ( LEqual (Arg0, 0) , LEqual (Arg1, 1) ) ) {
- //
- // Compatible PIO timing support
- //
- Return (900)
- }
- }
-
- //
- // Using ISP and RCT timing , PCI Clock = 33 Mhz , 30ns per clock
- //
- Return (Multiply(30,Subtract(9,Add(Arg2,Arg3))))
- }
- //
- // Get DMA Timing
- // Arg0 UDMA Supported
- // Arg1 Ata100
- // Arg2 Ata66/33
- // Arg3 Cable report / SATA No mater this input
- // Arg4 Cycle Timing
- //
- Method(GDMA,5)
- {
- //
- // Ultra DMA 66 & 100 need 80 pin conductor
- //
- If (LEqual (Arg0, 1)) {
- //
- // Ultra DMA Support
- //
- If (LEqual (Arg1, 1)) {
- //
- // ATA100 80 pin conducter support , Ultra DMA 5 Support
- //
- If (LEqual (Arg4, 2)) {
- Return (15)
- }
- Return (20)
-
- }
- If (LEqual (Arg2, 1)) {
- //
- // ATA66 80 pin conducter support , Base Clock 66Mhz , 15ns
per clock
- //
- Return (Multiply(15,Subtract(4,Arg4)))
- }
- //
- // Else Ultra DMA33Mhz Supported only,Base Clock 33Mhz , 30ns per
clock
- //
- Return (Multiply(30,Subtract(4,Arg4)))
- }
- // Doesnt support DMA mode
-
- Return (0xFFFFFFFE)
- }
- //
- // Set Flag
- // Arg0 IORDY for drive 0
- // Arg1 Ultra DMA for drive 0
- // Arg2 IORDY for drive 1
- // Arg3 Ultra DMA for drive 1
- // Arg4 indicates chipset can set timing independently for each drive
- //
- Method(SFLG, 5)
- {
- //
- // The Chipset always support separate timing setting and always
support IORDY
- //
- Store (0, Local0)
- Or (Arg1 ,Local0,Local0)
- Or (ShiftLeft (Arg0,1) ,Local0, Local0)
- Or (ShiftLeft (Arg2,3) ,Local0, Local0)
- Or (ShiftLeft (Arg3,2) ,Local0, Local0)
- Or (ShiftLeft (Arg4,4) ,Local0, Local0)
- Return (Local0)
- }
- //
- // Set PIO Timing
- // Arg0 Timing
- // Arg1 ATA Device PIO Mode Supported Flag
- // Arg2 ATA Device PIO Mode Supported Timing
- //
- // PIO/Mode Timing
- // PIO0/Compatible 900 ns
- // PIO2/SW2 240 ns
- // PIO3/MW1 180 ns
- // PIO4/MW2 120 ns
- //
-
- Method(SPIO , 3)
- {
- Name(PBUF, Buffer(5) { 0x00,0x00,0x00,0x00,0x00})
- CreateByteField(PBUF, 0, RCT)
- CreateByteField(PBUF, 1, ISP)
- CreateByteField(PBUF, 2, FAST)
- CreateByteField(PBUF, 3, DMAE)
- CreateByteField(PBUF, 4, PIOT)
- If (LOr (LEqual (Arg0, 0x0), LEqual (Arg0, 0x0FFFFFFFF)) ) {
-
- Return (PBUF)
- }
- If (LGreater (Arg0, 240)) {
- //
- // Compatible timing
- //
- Store (1, DMAE) // PIO Mode 0
- Store (0, PIOT) // Set to PIO Mode 0
-
- } Else {
- //
- // Fast Timing Enable
- //
- Store (1, FAST)
-
- If (And (Arg1, 0x002)) {
- //
- // ATA Device Supported PIO Mode Report
- //
- If (And (LEqual (Arg0, 120), And( Arg2 , 0x002) ) ) {
- //
- // Device support PIO Mode 4
- //
- Store (3, RCT) // RCT = 1 CLK
- Store (2, ISP) // ISP = 3 CLK
- Store (4, PIOT) // Set to PIO Mode 4
- } Else {
- If (And (LLessEqual (Arg0, 180), And( Arg2 , 0x001) ) ) {
- //
- // Device support PIO Mode 3
- //
- Store (1, RCT) // RCT = 3 CLK
- Store (2, ISP) // ISP = 3 CLK
- Store (3, PIOT) // Set to PIO Mode 3
- } Else {
- //
- // PIO Mode 2
- //
- Store (0, RCT) // RCT = 4 CLK
- Store (1, ISP) // ISP = 4 CLK
- Store (2, PIOT) // Set to PIO Mode 2
- }
- }
- }
- }
- Return (PBUF)
- }
- //
- // Set DMA Timing
- // Arg0 Timing
- // Arg1 ATA Device PIO Mode Supported Flag
- // Arg2 ATA Device PIO Mode Supported Timing
- //
- // UDMA/Mode Timing
- // UDMA5 20 ns
- // UDMA4 30 ns
- // UDMA3 45 ns
- // UDMA2 60 ns
- // UDMA1 90 ns
- // UDMA0 120 ns
- //
-
- Method(SDMA , 3)
- {
- Name(PBUF, Buffer(5) { 0x00,0x00,0x00,0x00})
- CreateByteField(PBUF, 0, PCT)
- CreateByteField(PBUF, 1, PCB)
- CreateByteField(PBUF, 2, UDMT) // ATA 100 Support
- CreateByteField(PBUF, 3, UDME) // Ultra DMA Enable
- CreateByteField(PBUF, 4, DMAT)
- If (LOr (LEqual (Arg0, 0x0), LEqual (Arg0, 0x0FFFFFFFF)) ) {
-
- Return (PBUF)
- }
- If (LLessEqual (Arg0, 120)) {
- //
- // Ultra DMA Supported
- //
- If (And (Arg1, 0x004)) {
- //
- // ATA Device Supported UDMA Mode Report
- //
- Store (1, UDME)
- If (And (LEqual (Arg0, 15), And( Arg2 , 0x0040) ) ) {
- //
- // Ultra DMA 6
- //
- Store (1, UDMT)
- Store (1, PCB)
- Store (2, PCT)
- Store (6, DMAT) // Set to UDMA Mode 6
- } Else {
- If (And (LEqual (Arg0, 20), And( Arg2 , 0x0020) ) ) {
- //
- // Ultra DMA 5
- //
- Store (1, UDMT)
- Store (1, PCB)
- Store (1, PCT)
- Store (5, DMAT) // Set to UDMA Mode 5
- } Else {
-
- If (And (LLessEqual (Arg0, 30), And( Arg2 , 0x00010) ) ) {
- //
- // Ultra DMA 4
- //
- Store (1, PCB)
- Store (2, PCT)
- Store (4, DMAT) // Set to UDMA Mode 4
-
- } Else {
-
- If (And (LLessEqual (Arg0, 45), And( Arg2 , 0x0008) ) ) {
- //
- // Ultra DMA 3
- //
- Store (1, PCB)
- Store (1, PCT)
- Store (3, DMAT) // Set to UDMA Mode 3
-
- } Else {
-
- If (And (LLessEqual (Arg0, 60), And( Arg2 , 0x0004) ) ) {
- //
- // Ultra DMA 2
- //
- Store (2, PCT)
- Store (2, DMAT) // Set to UDMA Mode 2
- } Else {
-
- If (And (LLessEqual (Arg0, 90), And( Arg2 , 0x0002) ) ) {
- //
- // Ultra DMA 1
- //
- Store (1, PCT)
- Store (1, DMAT) // Set to UDMA Mode 1
- } Else {
-
- If (And (LLessEqual (Arg0, 120), And( Arg2 , 0x0001) ) ) {
- //
- // Ultra DMA 0
- //
- Store (0, DMAT) // Set to UDMA Mode 0
- }
- }}}}}}
- }
- }
- Return (PBUF)
- }
-
-
- //
- // Primary ide channel
- //
- Device(PRID)
- {
- Name(_ADR,0)
- Name(TDM0, 0) // Drive 0 Ultra DMA Type
- Name(TPI0, 0) // Drive 0 PIO Type
- Name(TDM1, 0) // Drive 1 Ultra DMA Type
- Name(TPI1, 0) // Drive 1 PIO Type
-
- Method(_GTM)
- {
- Name(PBUF, Buffer(20) { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00 })
-
- CreateDwordField(PBUF, 0, PIO0)
- CreateDwordField(PBUF, 4, DMA0)
- CreateDwordField(PBUF, 8, PIO1)
- CreateDwordField(PBUF, 12, DMA1)
- CreateDwordField(PBUF, 16, FLAG)
-
- Store ( GPIO (PFT0, PDE0, PRT0, PIP0 ), PIO0)
- //
- // Setting the Drive1 PIO Timing, check if we use the same timging
for
- // both Drive0 and Drive1, and if the Drive0 is attached, else use
- // separate timing
- //
-
- If ( And (PSIT, 1) ) {
- Store ( GPIO (PFT1, PDE1, PRT1, PIP1 ), PIO1)
- } Else {
- Store ( GPIO (PFT1, PDE1, PRT0, PIP0 ), PIO1)
- }
-
- If (LEqual (PIO0, 0xFFFFFFFF)) {
- Store(PIO0, DMA0)
- } Else {
- Store ( GDMA(UDM0, PUM0, PCB0,And (PCCR ,0x1), PCT0) , DMA0)
- If ( LGreater ( DMA0, PIO0)) {
- Store(PIO0, DMA0)
- }
- }
- If (LEqual (PIO1, 0xFFFFFFFF)) {
- Store(PIO1, DMA1)
- } Else {
- Store ( GDMA(UDM1, PUM1, PCB1,And (PCCR ,0x2), PCT1) , DMA1)
- If ( LGreater ( DMA1, PIO1)) {
- Store(PIO1, DMA1)
- }
- }
- Store (SFLG (PIE0, UDM0, PIE1, UDM1, 1), FLAG)
-
- Return (PBUF)
- }
-
- Method(_STM,3)
- {
- CreateDwordField(Arg0, 0, PIO0)
- CreateDwordField(Arg0, 4, DMA0)
- CreateDwordField(Arg0, 8, PIO1)
- CreateDwordField(Arg0, 12, DMA1)
- CreateDwordField(Arg0, 16, FLAG)
-
- //
- // Device 0 Raw data
- //
- CreateWordField(Arg1, 106, RPS0) // word 53
- CreateWordField(Arg1, 128, IOM0) // word 64
- CreateWordField(Arg1, 176, DMM0) // Word 88
-
- //
- // Device 1 Raw data
- //
- CreateWordField(Arg2, 106, RPS1) // word 53
- CreateWordField(Arg2, 128, IOM1) // word 64
- CreateWordField(Arg2, 176, DMM1) // Word 88
-
- Name(IOTM, Buffer(5) { 0x00,0x00,0x00,0x00})
-
- CreateByteField(IOTM, 0, RCT)
- CreateByteField(IOTM, 1, ISP)
- CreateByteField(IOTM, 2, FAST)
- CreateByteField(IOTM, 3, DMAE)
- CreateByteField(IOTM, 4, TPIO) // PIO Type
-
- Name(DMAT, Buffer(5) { 0x00,0x00,0x00,0x00})
-
- CreateByteField(DMAT, 0, PCT)
- CreateByteField(DMAT, 1, PCB)
- CreateByteField(DMAT, 2, UDMT) // ATA 100 Support
- CreateByteField(DMAT, 3, UDME) // Ultra DMA Enable
- CreateByteField(DMAT, 4, TDMA) // UDMA Type
-
- If (And (FLAG , 0x10)) {
- Store (1, PSIT)
- }
-
- Store (SPIO (PIO0,RPS0,IOM0), IOTM)
-
- If (Or (DMAE, FAST)) {
- Store (RCT, PRT0)
- Store (ISP, PIP0)
- Store (FAST, PFT0)
- Store (DMAE, PDE0)
- Store (TPIO, TPI0)
- }
- Store (SPIO (PIO1,RPS1,IOM1), IOTM)
-
- If (Or (DMAE, FAST)) {
- Store (FAST, PFT1)
- Store (DMAE, PDE1)
- Store (TPIO, TPI1)
- If (And (PSIT,1)) {
- //
- // Need set Drive 1 PIO Timing seperate
- //
- Store (RCT, PRT1)
- Store (ISP, PIP1)
- } Else {
- Store (RCT, PRT0)
- Store (ISP, PIP0)
- }
- }
- If (And (FLAG , 0x01)) {
- Store (SDMA (DMA0,RPS0,DMM0), DMAT)
- Store (PCT , PCT0)
- Store (PCB , PCB0)
- Store (UDME, UDM0)
- Store (UDMT, PUM0)
- Store (TDMA, TDM0)
- } Else {
- Store (0, UDM0)
- }
-
- If (And (FLAG , 0x04)) {
- Store (SDMA (DMA1,RPS1,DMM1), DMAT)
- Store (PCT , PCT1)
- Store (PCB , PCB1)
- Store (UDME, UDM1)
- Store (UDMT, PUM1)
- Store (TDMA, TDM1)
- } Else {
- Store (0, UDM1)
- }
- //
- // Check IORDY Support
- //
- If (And (FLAG , 0x2)) {
- Store (1 , PIE0)
- }
- If (And (FLAG , 0x8)) {
- Store (1 , PIE1)
- }
-
- }
- Device(MAST)
- {
- Name(_ADR,0)
- Method(_GTF)
- {
- //
- // Set ATA Device to corresponding Mode
- //
- Name(ATA0, Buffer(14)
- { 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF,
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF })
-
- CreateByteField(ATA0,1,PIO0) // PIO0 = PIO Mode, Drive 0
- CreateByteField(ATA0,8,DMA0) // DMA0 = DMA Mode, Drive 0
-
-
- Store (TPI0, PIO0) // Type we Already get
-
- Or (PIO0, 0x08 ,PIO0)
-
- If ( And (UDM0, 1)) {
- Store (TDM0, DMA0) // Ultra DMA
- Or (DMA0, 0x40, DMA0)
- } Else {
- Store (TPI0, DMA0) // Use PIO Timing
- If ( LNotEqual (DMA0, 0)) {
- Subtract(DMA0, 2, DMA0)
- }
- Or (DMA0, 0x20, DMA0)
- }
- Return (ATA0)
- }
- }
- Device(SLAV)
- {
- Name(_ADR,1)
- Method(_GTF)
- {
- //
- // Set ATA Device to corresponding Mode
- //
- Name(ATA1, Buffer(14)
- { 0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF,
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF })
-
- CreateByteField(ATA1,1,PIO1) // PIO0 = PIO Mode, Drive 0
- CreateByteField(ATA1,8,DMA1) // DMA0 = DMA Mode, Drive 0
-
- Store (TPI1, PIO1) // Type we Already get
-
- Or (PIO1, 0x08 ,PIO1)
-
- If ( And (UDM1, 1)) {
- Store (TDM1, DMA1) // Ultra DMA
- Or (DMA1, 0x40, DMA1)
- } Else {
- Store (TPI1, DMA1) // Use PIO Timing
- If ( LNotEqual (DMA1, 0)) {
- Subtract(DMA1, 2, DMA1)
- }
- Or (DMA1, 0x20, DMA1)
- }
- Return(ATA1)
- }
- }
- }
- //
- // Secondary SATA channel
- //
- Device(SECD)
- {
- Name(_ADR,1)
- Name(TDM0, 0)
- Name(TPI0, 0)
- Name(TDM1, 0)
- Name(TPI1, 0)
-
- Name(DMT1, Buffer(5) { 0x00,0x00,0x00,0x00})
- Name(DMT2, Buffer(5) { 0x00,0x00,0x00,0x00})
- Name(POT1, Buffer(5) { 0x00,0x00,0x00,0x00})
- Name(POT2, Buffer(5) { 0x00,0x00,0x00,0x00})
-
- Name(STMI, Buffer(20) { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00 })
-
- Method(_GTM)
- {
- Name(PBUF, Buffer(20) { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00 })
-
- CreateDwordField(PBUF, 0, PIO0)
- CreateDwordField(PBUF, 4, DMA0)
- CreateDwordField(PBUF, 8, PIO1)
- CreateDwordField(PBUF, 12, DMA1)
- CreateDwordField(PBUF, 16, FLAG)
-
- Store ( GPIO (SFT0, SDE0, SRT0, SIP0 ), PIO0)
- //
- // Setting the Drive1 PIO Timing, check if we use the same timging
for
- // both Drive0 and Drive1, and if the Drive0 is attached, else use
- // separate timing
- //
- If ( And (SSIT, 1) ) {
- Store ( GPIO (SFT1, SDE1, SRT1, SIP1 ), PIO1)
- } Else {
- Store ( GPIO (SFT1, SDE1, SRT0, SIP0 ), PIO1)
- }
-
- If (LEqual (PIO0, 0xFFFFFFFF)) {
- Store(PIO0, DMA0)
- } Else {
- Store ( GDMA(UDM2, SUM0, SCB0,And (SCCR ,0x1), SCT0) , DMA0)
- If ( LGreater ( DMA0, PIO0)) {
- Store(PIO0, DMA0)
- }
- }
-
- If (LEqual (PIO1, 0xFFFFFFFF)) {
- Store(PIO1, DMA1)
- } Else {
- Store ( GDMA(UDM3, SUM1, SCB1,And (SCCR ,0x2), SCT1) , DMA1)
- If ( LGreater ( DMA1, PIO1)) {
- Store(PIO1, DMA1)
- }
- }
-
- Store (SFLG (SIE0, UDM2, SIE1, UDM3, 1), FLAG)
-
- Return (PBUF)
- }
- Method(_STM,3)
- {
- CreateDwordField(Arg0, 0, PIO0)
- CreateDwordField(Arg0, 4, DMA0)
- CreateDwordField(Arg0, 8, PIO1)
- CreateDwordField(Arg0, 12, DMA1)
- CreateDwordField(Arg0, 16, FLAG)
-
- Store (Arg0, STMI)
- //
- // Device 0 Raw data
- //
- CreateWordField(Arg1, 106, RPS0) // word 53
- CreateWordField(Arg1, 128, IOM0) // word 64
- CreateWordField(Arg1, 176, DMM0) // Word 88
-
- //
- // Device 1 Raw data
- //
- CreateWordField(Arg2, 106, RPS1) // word 53
- CreateWordField(Arg2, 128, IOM1) // word 64
- CreateWordField(Arg2, 176, DMM1) // Word 88
-
- Name(IOTM, Buffer(5) { 0x00,0x00,0x00,0x00})
-
- CreateByteField(IOTM, 0, RCT)
- CreateByteField(IOTM, 1, ISP)
- CreateByteField(IOTM, 2, FAST)
- CreateByteField(IOTM, 3, DMAE)
- CreateByteField(IOTM, 4, TPIO) // PIO Type
-
- Name(DMAT, Buffer(5) { 0x00,0x00,0x00,0x00})
-
- CreateByteField(DMAT, 0, PCT)
- CreateByteField(DMAT, 1, PCB)
- CreateByteField(DMAT, 2, UDMT) // ATA 100 Support
- CreateByteField(DMAT, 3, UDME) // Ultra DMA Enable
- CreateByteField(DMAT, 4, TDMA) // UDMA Type
-
- If (And (FLAG , 0x10)) {
- Store (1, SSIT)
- }
-
- //
- // Get Timing and Flag Setting
- //
- Store (SPIO (PIO0,RPS0,IOM0), IOTM)
- //
- // If no drive0 connect, do nothing to program Drive0 timing
- //
- If (Or (DMAE, FAST)) {
- Store (RCT, SRT0)
- Store (ISP, SIP0)
- Store (FAST, SFT0)
- Store (DMAE, SDE0)
- Store (TPIO, TPI0)
- }
-
- Store (SPIO (PIO1,RPS1,IOM1), IOTM)
-
- Store (IOTM,POT2)
-
- If (Or (DMAE, FAST)) {
- Store (FAST, SFT1)
- Store (DMAE, SDE1)
- Store (TPIO, TPI1)
- If (And (SSIT,1)) {
- //
- // Need set Drive 1 PIO Timing separately
- //
- Store (RCT, SRT1)
- Store (ISP, SIP1)
- } Else {
- Store (RCT, SRT0)
- Store (ISP, SIP0)
- }
- }
-
- If (And (FLAG , 0x01)) {
- Store (SDMA (DMA0,RPS0,DMM0), DMAT)
- Store (PCT , SCT0)
- Store (PCB , SCB0)
- Store (UDME , UDM2)
- Store (UDMT , SUM0)
- Store (TDMA, TDM0)
- } Else {
- Store (0, UDM2)
- }
- If (And (FLAG , 0x04)) {
- Store (SDMA (DMA1,RPS1,DMM1), DMAT)
- Store (PCT , SCT1)
- Store (PCB , SCB1)
- Store (UDME , UDM3)
- Store (UDMT , SUM1)
- Store (TDMA , TDM1)
- } Else {
- Store (0, UDM3)
- }
- //
- // Check IORDY Support
- //
- If (And (FLAG , 0x2)) {
- Store (1 , SIE0)
- }
- If (And (FLAG , 0x8)) {
- Store (1 , SIE1)
- }
-
- }
- Device(MAST)
- {
- Name(_ADR,0)
- Method(_GTF)
- {
- //
- // Set ATA Device to corresponding Mode
- //
- Name(ATA0, Buffer(14)
- { 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF,
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xA0, 0xEF })
-
- CreateByteField(ATA0,1,PIO0) // PIO0 = PIO Mode, Drive 0
- CreateByteField(ATA0,8,DMA0) // DMA0 = DMA Mode, Drive 0
-
- Store (TPI0, PIO0) // Type we Already get
-
- Or (PIO0, 0x08 ,PIO0)
-
- If ( And (UDM2, 1)) {
- Store (TDM0, DMA0) // Ultra DMA
- Or (DMA0, 0x40, DMA0)
- } Else {
- Store (TPI0, DMA0) // Use PIO Timing
- If ( LNotEqual (DMA0, 0)) {
- Subtract(DMA0, 2, DMA0)
- }
- Or (DMA0, 0x20, DMA0)
- }
- Return (ATA0)
- }
- }
- Device(SLAV)
- {
- Name(_ADR,1)
- Method(_GTF)
- {
- //
- // Set ATA Device to corresponding Mode
- //
- Name(ATA1, Buffer(14)
- { 0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF,
- 0x03, 0x00, 0x00, 0x00, 0x00, 0xB0, 0xEF })
-
- CreateByteField(ATA1,1,PIO1) // PIO0 = PIO Mode, Drive 0
- CreateByteField(ATA1,8,DMA1) // DMA0 = DMA Mode, Drive 0
-
- Store (TPI1, PIO1) // Type we Already get
-
- Or (PIO1, 0x08 ,PIO1)
-
- If ( And (UDM3, 1)) {
- Store (TDM1, DMA1) // Ultra DMA
- Or (DMA1, 0x40, DMA1)
- } Else {
- Store (TPI1, DMA1) // Use PIO Timing
- If ( LNotEqual (DMA1, 0)) {
- Subtract(DMA1, 2, DMA1)
- }
- Or (DMA1, 0x20, DMA1)
- }
- Return(ATA1)
- }
- }
- }
diff --git
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchXhci.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchXhci.asi
deleted file mode 100644
index d2563e0487..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PchXhci.asi
+++ /dev/null
@@ -1,329 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-Name (OPAC, Zero)
-Name (XRST, Zero)
-Name (XUSB, Zero)
-
-OperationRegion (XPRT, PCI_Config, 0x74, 0x6C)
-Field (XPRT, DWordAcc, NoLock, Preserve)
-{
- , 8,
- PMEE, 1, // PWR_CNTL_STS.PME_En
- , 6,
- PMES, 1, // PWR_CNTL_STS.PME_Sts
- Offset (0x5C),
- PR2, 32, // XUSB2PR: xHC USB 2.0 Port Routing Register.
- PR2M, 32, // XUSB2PRM: xHC USB 2.0 Port Routing Mask Register.
- PR3, 32, // USB3_PSSEN: USB3.0 Port SuperSpeed Enable Register.
- PR3M, 32 // USB3PRM: USB3.0 Port Routing Mask Register
-}
-
-Method (_PSW,1)
-{
- If (Arg0)
- {
- Store (Ones,PMEE)
- }
- Else
- {
- Store (0,PMEE)
- }
-}
-
-
-//
-// Indicate access to OperationRegions is enabled/disabled
-//
-Method (_REG, 2) {
- //
- // If OperationRegion ID = PCI_Config
- //
- If (LEqual (Arg0, 2)) {
- //
- // If access is enabled
- //
- If (LEqual(Arg1, 1)) {
- //
- // Set local flag
- //
- Store (One, OPAC)
-
- } Else {
- //
- // Clear local flag
- //
- Store (One, OPAC)
- }
- }
-}
-
-//
-// Initialization for this controller
-//
-Method (_INI, 0) {
- //
- // If access to OperationRegion is enabled
- //
- If (LEqual (OPAC, One)) {
- Store (1, PMES) // clear PME status
- Store (0, PMEE) // clear PME enable
- }
-}
-
-//
-// _OSC for xHCI
-// This method enables XHCI controller if available.
-//
-// Arguments:
-// Arg0 (Integer): Revision ID - should be set to 1
-//
-// Arg1 (Integer): Count of DWords in Arg3
-//
-// Arg2 (Buffer) : Capabilities Buffer
-// DWORD #0 (Status/Error):
-// Bit 0 - Query Support Flag
-// Bit 1 - Always clear(0)
-// Bit 2 - Always clear(0)
-// Bit 3 - Always clear(0)
-//
-// All others - reserved
-//
-// DWORD #1 (Supported):
-// Bit 0 - 1: Switch to xHCI
-//
-// All others - reserved
-//
-// DWORD #2 (Controlled):
-// Bit 0 - 1: Clear Smart Auto state (disable xHCI)
-//
-// All others - reserved
-//
-// Returns:
-// Capabilities Buffer:
-// DWORD #0 (Status):
-// Bit 0 - Reserved (not used)
-//
-// Bit 1 - _OSC failure. Platform Firmware was unable to
process the request or query.
-// Capabilities bits may have been masked.
-//
-// Bit 2 - Unrecognized UUID. This bit is set to indicate
that the platform firmware
-// does not recognize the UUID passed in _OSC Arg0.
-// Capabilities bits are preserved.
-//
-// Bit 3 - Unrecognized Revision. This bit is set to indicate
that the platform firmware
-// does not recognize the Revision ID passed in via
Arg1.
-// Capabilities bits beyond those comprehended by the
firmware will be masked.
-//
-// Bit 4 - Capabilities Masked. This bit is set to indicate
-// that capabilities bits set by driver software
-// have been cleared by platform firmware.
-//
-// Bit 5 - 0: EHCI controller exposed to OS
-// 1: xHCI controller exposed to OS
-//
-// All others - reserved (return 0)
-//
-// DWORD #1 (Supported):
-// Bit 0 - 0: EHCI supported
-// 1: xHCI supported
-//
-// All others - reserved
-//
-// DWORD #2 (Controlled):
-//
-// All bits - reserved
-//
-
-Method (POSC, 3) {
-
- Store (0x81, IO80)
-
- //
- // Create DWord fields from the Capabilities Buffer
- //
- CreateDWordField (Arg2, 0, CDW1) // CDW1 = DWORD that starts at offset 0
of Arg2
- CreateDWordField (Arg2, 4, CDW2) // CDW2 = DWORD that starts at offset 4
of Arg2
- CreateDWordField (Arg2, 8, CDW3) // CDW3 = DWORD that starts at offset 8
of Arg2
-
- //
- // Are we running a version of Windows that runs the Intel xHCI driver?
- // i.e. Windows Server 2008 through Windows Server 2008 R2 & Windows 7
- //
- If (LAnd (LGreaterEqual (\_SB.OSYS, 9), LLessEqual (\_SB.OSYS, 12))) {
- //
- // Running Windows
- // Check revision is >= 2
- //
- If (LLess (Arg0, 2)) {
- //
- // Set unknown revision bit
- //
- Or (CDW1, 8, CDW1)
- Store (0x82, IO80)
- }
- } Else {
- //
- // If the Intel xHCI driver not calling,
- // then it must be SVOS
- If (LNotEqual (Arg0, 1)) {
- //
- // Set unknown revision bit
- //
- Or (CDW1, 8, CDW1)
- Store (0x82, IO80)
- }
- }
-
- //
- // Set failure if xHCI is disabled by BIOS
- //
- If (LEqual (XHMD, 0)) {
- Or (CDW1, 2, CDW1)
- Store (0x83, IO80)
- }
-
- //
- // If no error bits set
- //
- If (LEqual (And (CDW1, 0xE), 0)) {
- //
- // If not just querying support
- //
- If (LNot (And (CDW1, 1))) {
- //
- // If uninstaller calling
- // to switch back to EHCI
- //
- If (And (CDW3, 1)) {
- //
- // Switch to EHCI
- //
- ESEL()
- Store (0x85, IO80)
-
- //
- // And clear ACPINVS variable
- // that is a copy of USB3.0 setup option
- // so that we will not re-enable xHCI until
- // the next reboot
- //
- Store (0, XHMD)
- }
-
- //
- // Uninstaller not calling,
- // OS wants to enable xHCI?
- //
- If (And (CDW2, 1)) {
- //
- // Switch to xHCI
- //
- XSEL(0)
- Store (0x84, IO80)
- } Else {
- //
- // Switch to EHCI
- //
- ESEL()
- Store (0x85, IO80)
- }
- }
- }
-
- Return(Arg2)
-}
-
-//
-// Put all ports in XHCI mode
-//
-Method (XSEL, 1, Serialized) {
- //
- // If xHCI in auto or smart auto mode
- // or Arg0 == 1
- //
- If ( LOr (LOr (LEqual (XHMD, 2), LEqual (XHMD, 3)), Arg0) ) {
- //
- // If xHCI in smart auto mode
- //
- If (LEqual (XHMD, 3)) {
- //
- // Set B0:D31:F0 ACh[16] to indicate OS has routed ports to xHCI
controller
- //
- Store (1, \_SB.PC00.LPC0.XSMB)
- }
-
- //
- // Set flags so on Sx resume, we'll know OS has previously
- // routed ports to xHCI
- //
- Store (1, XUSB)
- Store (1, XRST) // Backup XUSB, cause it might lost in iRST G3 or DeepSx
-
- //
- // Enable selected SS ports, route corresponding HS ports to xHCI
- //
- Store (0, Local0)
- And (PR3, 0xFFFFFFC0, Local0)
- Or (Local0, PR3M, PR3)
- Store (0, Local0)
- And (PR2, 0xFFFF8000, Local0)
- Or (Local0, PR2M, PR2)
- }
-}
-
-//
-// Put all ports in EHCI mode
-//
-Method (ESEL, 0, Serialized) {
- //
- // xHCI in auto or smart auto mode
- //
- If (LOr (LEqual (XHMD, 2), LEqual (XHMD, 3))) {
- //
- // Disable all SS ports, route all HS ports to EHCI
- //
- And (PR3, 0xFFFFFFC0, PR3)
- And (PR2, 0xFFFF8000, PR2)
-
- //
- // Mark as not routed.
- //
- Store (0, XUSB)
- Store (0, XRST)
- }
-}
-
-Method (XWAK, 0, Serialized) {
- //
- // If ports were routed to xHCI before sleep
- //
- If (LOr (LEqual (XUSB, 1), LEqual (XRST, 1))) {
- //
- // Restore back to xHCI, ignore XHMD
- //
- XSEL(1)
-
- //
- // And tell OS to re-enumerate xHCI
- //
- Notify (\_SB.PC00.XHCI, 0x00)
- }
-}
-
-//
-// Report what D state the controller is in
-// when the system changes to S3 and S4
-//
-Method(_S3D, 0, NotSerialized) {
- Return(2)
-}
-
-Method(_S4D, 0, NotSerialized) {
- Return(2)
-}
-
diff --git
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciCrs.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciCrs.asi
deleted file mode 100644
index 6fb2cb589d..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciCrs.asi
+++ /dev/null
@@ -1,312 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-// Return the proximity domain/node # that this bus is on
-// With this info OSPM will know what memory and I/O resources
-// are under the same IOH
-//
-Name(_PXM, 0)
-
-#define RESOURCE_CHUNK1_OFF 0
-#define RESOURCE_CHUNK2_OFF 16 //(RESOURCE_CHUNK1_OFF + 16)
-#define RESOURCE_CHUNK3_OFF 24 //(RESOURCE_CHUNK2_OFF + 8)
-#define RESOURCE_CHUNK4_OFF 40 //(RESOURCE_CHUNK3_OFF + 16)
-#define RESOURCE_CHUNK5_OFF 56 //(RESOURCE_CHUNK4_OFF + 16)
-#define RESOURCE_CHUNK6_OFF 82 //(RESOURCE_CHUNK5_OFF + 26)
-#define RESOURCE_CHUNK7_OFF 108 //(RESOURCE_CHUNK6_OFF + 26)
-
-#define PciResourceStart Local0
-#define PciResourceLen Local1
-
-Name(PBRS, ResourceTemplate() {
- //RESOURCE_CHUNK1_OFF
- WORDBusNumber( //Bus number resource (0); the bridge produces bus
numbers for its subsequent buses
- ResourceProducer, // bit 0 of general flags is 1
- MinFixed, // Range is fixed
- MaxFixed, // Range is fixed
- PosDecode, // PosDecode
- 0x0000, // Granularity
- 0x0000, // Min
- 0x0000, // Max
- 0x0000, // Translation
- 0x0000,,, // Range Length = Max-Min+1
- PB00
- )
-
- //RESOURCE_CHUNK2_OFF
- IO( //Consumed resource (CF8-CFF)
- Decode16,
- 0x0cf8,
- 0xcf8,
- 1,
- 8
- )
-
- //RESOURCE_CHUNK3_OFF
- WORDIO( //Consumed-and-produced resource (all I/O below
CF8)
- ResourceProducer, // bit 0 of general flags is 0
- MinFixed, // Range is fixed
- MaxFixed, // Range is fixed
- PosDecode,
- EntireRange,
- 0x0000, // Granularity
- 0x0000, // Min
- 0x0cf7, // Max
- 0x0000, // Translation
- 0x0cf8 // Range Length
- )
-
- //RESOURCE_CHUNK4_OFF
- WORDIO( //Consumed-and-produced resource (all I/O above
CFF)
- ResourceProducer, // bit 0 of general flags is 0
- MinFixed, // Range is fixed
- MaxFixed, // Range is fixed
- PosDecode,
- EntireRange,
- 0x00, // Granularity
- 0x0000, // Min
- 0x0000, // Max
- 0x00, // Translation
- 0x0000,,, // Range Length
- PI01
- )
-
- //RESOURCE_CHUNK5_OFF
- DWORDMEMORY( // descriptor for video RAM on video card
- ResourceProducer, // bit 0 of general flags is 0
- PosDecode,
- MinFixed, // Range is fixed
- MaxFixed, // Range is fixed
- Cacheable,
- ReadWrite,
- 0x00000000, // Granularity
- 0x000a0000, // Min
- 0x000bffff, // Max
- 0x00000000, // Translation
- 0x00020000 // Range Length
- )
-
- //RESOURCE_CHUNK6_OFF
- DWORDMEMORY( // descriptor for Shadow RAM
- ResourceProducer, // bit 0 of general flags is 0
- PosDecode,
- MinFixed, // Range is fixed
- MaxFixed, // Range is fixed
- Cacheable,
- ReadWrite,
- 0x00000000, // Granularity
- 0x00000000, // Min (calculated dynamically)
- 0x00000000, // Max (calculated dynamically)
- 0x00000000, // Translation
- 0x00000000,,, // Range Length (calculated dynamically)
- SDRM
- )
-
- //RESOURCE_TPM
- DWORDMemory( // Consumed-and-produced resource(all of memory
space)
- ResourceProducer, // bit 0 of general flags is 0
- PosDecode, // positive Decode
- MinFixed, // Range is fixed
- MaxFixed, // Range is fixed
- NonCacheable,
- ReadWrite,
- 0x00000000, // Granularity
- 0xFED40000, // Min (calculated dynamically)
- 0xFEDFFFFF, // Max = 4GB - 1MB (fwh + fwh alias...)
- 0x00000000, // Translation
- 0x000C0000 // Range Length (calculated dynamically)
- )
-
- //
- // PCI RESOURCE_32bit
- //
- DWORDMemory( // Consumed-and-produced resource(all of memory
space)
- ResourceProducer, // bit 0 of general flags is 0
- PosDecode, // positive Decode
- MinFixed, // Range is fixed
- MaxFixed, // Range is fixed
- NonCacheable,
- ReadWrite,
- 0x00, // Granularity
- 0x00000000, // Min (calculated dynamically)
- 0x00000000, // Max = 4GB - 1MB (fwh + fwh alias...)
- 0x00, // Translation
- 0x00000000,,, // Range Length (calculated dynamically)
- PM01
- )
-
- //
- // PCI RESOURCE_64bit
- //
- QWORDMemory( // Consumed-and-produced resource(all of memory
space)
- ResourceProducer, // bit 0 of general flags is 0
- PosDecode, // positive Decode
- MinFixed, // Range is fixed
- MaxFixed, // Range is fixed
- NonCacheable,
- ReadWrite,
- 0x00, // Granularity
- 0x00000000000, // Min (calculated dynamically)
- 0x00000000000, // Max = 4GB - 1MB (fwh + fwh alias...)
- 0x00, // Translation
- 0x00000000000,,, // Range Length (calculated dynamically)
- PM02
- )
-}) // end of PBRS Buffer
-
-
-Method(_CRS, 0x0, NotSerialized)
-{
- //calculate Shadow RAM
- EROM()
-
- // Fix up Bus Number Resources
- CreateWordField(PBRS, ^PB00._MIN, PBMN)
- Store(BBI0, PBMN)
- CreateWordField(PBRS, ^PB00._MAX, PBMX) // (MAX bus decoded - 1,
assuming Uncore Bus is MAX decoded BUS Number)
- Store(BBL0, PBMX)
- CreateWordField(PBRS, ^PB00._LEN, PBLN)
- Subtract(PBMX, PBMN, PBLN)
- Add(1, PBLN, PBLN)
-
- // Fix up 16-bit IO resources
- CreateWordField(PBRS, ^PI01._MIN, PIMN)
- Store(IOBA, PIMN)
- CreateWordField(PBRS, ^PI01._MAX, PIMX)
- Store(IOLA, PIMX)
- CreateWordField(PBRS, ^PI01._LEN, PILN)
- Subtract(PIMX, PIMN, PILN)
- Add(1, PILN, PILN)
-
- // Fix up 32-bit Memory resources
- CreateDWordField(PBRS, ^PM01._MIN, PMMN)
- Store(MMB0, PMMN)
- CreateDWordField(PBRS, ^PM01._MAX, PMMX)
- Store(MML0, PMMX)
- CreateDWordField(PBRS, ^PM01._LEN, PMLN)
- Subtract(PMMX, PMMN, PMLN)
- Add(1, PMLN, PMLN)
-
- // Fix up 64-bit Memory resources
-// If(LAnd(MMH0, LGreater(OSFL, 8))) {
- CreateQWordField(PBRS, ^PM02._MIN, P2MN)
- Store(HMB0, P2MN)
- CreateQWordField(PBRS, ^PM02._MAX, P2MX)
- Store(HML0, P2MX)
- CreateQWordField(PBRS, ^PM02._LEN, P2LN)
- Subtract(P2MX, P2MN, P2LN)
- Add(1, P2LN, P2LN)
-// }
-
- Return(PBRS)
-}
-
-Method(_STA,0) {
- If (NPB0) {
- Return(0x0F)
- }
- Return(0x00)
-}
-
-OperationRegion(TMEM, PCI_Config, 0x52, 0x3)
-Field(TMEM, ByteAcc, NoLock, Preserve) {
- DIM0, 4,
- DIM1, 4,
- , 8,
- DIM2, 4
-}
-
-Name(MTBL, Package(0x10) {
- 0x0,
- 0x20,
- 0x20,
- 0x30,
- 0x40,
- 0x40,
- 0x60,
- 0x80,
- 0x80,
- 0x80,
- 0x80,
- 0xc0,
- 0x100,
- 0x100,
- 0x100,
- 0x200
-})
-
-
-OperationRegion(PAMX, PCI_Config, 0x90, 0x7)
-Field(PAMX, ByteAcc, NoLock, Preserve) {
- , 4,
- BSEG, 4,
- PAMS, 48
-}
-
-Name(ERNG, Package(0xd) {
- 0xc0000,
- 0xc4000,
- 0xc8000,
- 0xcc000,
- 0xd0000,
- 0xd4000,
- 0xd8000,
- 0xdc000,
- 0xe0000,
- 0xe4000,
- 0xe8000,
- 0xec000,
- 0xf0000
-})
-
-Name(PAMB, Buffer(0x7) {
-})
-
-Method(EROM, 0x0, NotSerialized) {
- CreateDWordField(PBRS, 0x5c, RMIN)
- CreateDWordField(PBRS, 0x60, RMAX)
- CreateDWordField(PBRS, 0x68, RLEN)
- CreateByteField(PAMB, 0x6, BREG)
- Store(PAMS, PAMB)
- Store(BSEG, BREG)
- Store(0x0, RMIN)
- Store(0x0, RMAX)
- Store(0x0, RLEN)
- Store(0x0, Local0)
- While(LLess(Local0, 0xd)) {
- ShiftRight(Local0, 0x1, Local1)
- Store(DerefOf(Index(PAMB, Local1, )), Local2)
- If(And(Local0, 0x1, )) {
- ShiftRight(Local2, 0x4, Local2)
- }
- And(Local2, 0x3, Local2)
- If(RMIN) {
- If(Local2) {
- Add(DerefOf(Index(ERNG, Local0, )), 0x3fff, RMAX)
- If(LEqual(RMAX, 0xf3fff)) {
- Store(0xfffff, RMAX)
- }
- Subtract(RMAX, RMIN, RLEN)
- Increment(RLEN)
- } Else {
- Store(0xc, Local0)
- }
- } Else {
- If(Local2) {
- Store(DerefOf(Index(ERNG, Local0, )), RMIN)
- Add(DerefOf(Index(ERNG, Local0, )), 0x3fff, RMAX)
- If(LEqual(RMAX, 0xf3fff)) {
- Store(0xfffff, RMAX)
- }
- Subtract(RMAX, RMIN, RLEN)
- Increment(RLEN)
- } Else {
- }
- }
- Increment(Local0)
- }
-}
diff --git
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciIrq.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciIrq.asi
deleted file mode 100644
index fe7c2b8753..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PciIrq.asi
+++ /dev/null
@@ -1,455 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-OperationRegion (PRR0, PCI_Config, 0x00, 0x100)
-Field (PRR0, AnyAcc, NoLock, Preserve) {
- Offset(0x60),
- PIRA, 8,
- PIRB, 8,
- PIRC, 8,
- PIRD, 8,
- Offset(0x68),
- PIRE, 8,
- PIRF, 8,
- PIRG, 8,
- PIRH, 8
-}
-
-Device (LNKA) { // PCI IRQ link A
- Name (_HID,EISAID("PNP0C0F"))
- //Name(_UID, 1)
- Method (_STA,0,NotSerialized) {
- If(And(PIRA, 0x80)) {
- Return (0x9)
- } Else {
- Return (0xB)
- } // Don't display
- }
-
- Method (_DIS,0,NotSerialized) {
- Or (PIRA, 0x80, PIRA)
- }
-
- Method (_CRS,0,Serialized) {
- Name (BUF0, ResourceTemplate() {IRQ(Level,ActiveLow,Shared){0}})
- //
- // Define references to buffer elements
- //
- CreateWordField (BUF0, 0x01, IRQW) // IRQ low
- //
- // Write current settings into IRQ descriptor
- //
- If (And(PIRA, 0x80)) {
- Store (Zero, Local0)
- } Else {
- Store (One,Local0)
- }
- //
- // Shift 1 by value in register 70, Save in buffer
- //
- ShiftLeft (Local0,And (PIRA,0x0F),IRQW) // Save in buffer
- Return (BUF0) // Return Buf0
- } // End of _CRS method
-
- Name (_PRS, ResourceTemplate()
- {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
-
- Method (_SRS,1,NotSerialized) {
- CreateWordField (ARG0, 0x01, IRQW) // IRQ low
-
- FindSetRightBit(IRQW,Local0) // Set IRQ
- If (LNotEqual (IRQW,Zero)){
- And (Local0, 0x7F,Local0)
- Decrement (Local0)
- } Else {
- Or (Local0, 0x80,Local0)
- }
- Store (Local0, PIRA)
- } // End of _SRS Method
-}
-
-Device(LNKB) { // PCI IRQ link B
- Name (_HID,EISAID("PNP0C0F"))
- //Name(_UID, 2)
- Method (_STA,0,NotSerialized) {
- If (And (PIRB, 0x80)) {
- Return (0x9)
- } Else {
- Return (0xB)
- } // Don't display
- }
-
- Method (_DIS,0,NotSerialized) {
- Or (PIRB, 0x80,PIRB)
- }
-
- Method (_CRS,0,Serialized) {
- Name(BUF0, ResourceTemplate()
- {IRQ(Level,ActiveLow,Shared){0}})
- //
- // Define references to buffer elements
- //
- CreateWordField (BUF0, 0x01, IRQW) // IRQ low
- //
- // Write current settings into IRQ descriptor
- //
- If (And (PIRB, 0x80)) {
- Store (Zero, Local0)
- } Else {
- Store (One,Local0)
- }
- //
- // Shift 1 by value in register 70, Save in buffer
- //
- ShiftLeft (Local0,And (PIRB,0x0F),IRQW) // Save in buffer
- Return (BUF0) // Return Buf0
- } // End of _CRS method
-
- Name (_PRS,
- ResourceTemplate()
- {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
-
- Method (_SRS,1,NotSerialized) {
- CreateWordField (ARG0, 0x01, IRQW) // IRQ low
-
- FindSetRightBit(IRQW,Local0) // Set IRQ
- If (LNotEqual(IRQW,Zero)) {
- And (Local0, 0x7F, Local0)
- Decrement (Local0)
- } Else {
- Or (Local0, 0x80, Local0)
- }
- Store (Local0, PIRB)
- } // End of _SRS Method
-}
-
-Device(LNKC) { // PCI IRQ link C
- Name(_HID, EISAID("PNP0C0F"))
- //Name(_UID, 3)
-
- Method (_STA,0,NotSerialized) {
- If (And (PIRC, 0x80)) {
- Return (0x9)
- } Else {
- Return (0xB)
- } // Don't display
- }
-
- Method (_DIS, 0, NotSerialized) {
- Or (PIRC, 0x80, PIRC)
- }
-
- Method (_CRS, 0, Serialized) {
- Name (BUF0, ResourceTemplate()
- {IRQ(Level,ActiveLow,Shared){0}})
- //
- // Define references to buffer elements
- //
- CreateWordField (BUF0, 0x01, IRQW) // IRQ low
- //
- // Write current settings into IRQ descriptor
- //
- If (And (PIRC, 0x80)) {
- Store (Zero, Local0)
- } Else {
- Store (One,Local0)
- }
- //
- // Shift 1 by value in register 70, Save in buffer
- //
- ShiftLeft (Local0,And (PIRC,0x0F),IRQW)
- Return (BUF0)
- } // End of _CRS method
-
- Name (_PRS, ResourceTemplate()
- {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
-
- Method (_SRS,1,NotSerialized) {
- CreateWordField (ARG0, 0x01, IRQW) // IRQ low
- FindSetRightBit(IRQW,Local0) // Set IRQ
- If (LNotEqual (IRQW,Zero)) {
- And (Local0, 0x7F, Local0)
- Decrement (Local0)
- } Else {
- Or (Local0, 0x80,Local0)
- }
- Store (Local0, PIRC)
- } // End of _SRS Method
-}
-
-Device (LNKD) { // PCI IRQ link D
- Name (_HID,EISAID ("PNP0C0F"))
-
- //Name(_UID, 4)
-
- Method (_STA, 0, NotSerialized) {
- If (And (PIRD, 0x80)) {
- Return (0x9)
- } Else {
- Return (0xB)
- } // Don't display
- }
-
- Method (_DIS, 0, NotSerialized) {
- Or(PIRD, 0x80,PIRD)
- }
-
- Method (_CRS,0,Serialized) {
- Name (BUF0, ResourceTemplate()
- {IRQ(Level,ActiveLow,Shared){0}})
- //
- // Define references to buffer elements
- //
- CreateWordField (BUF0, 0x01, IRQW) // IRQ low
- //
- // Write current settings into IRQ descriptor
- //
- If (And (PIRD, 0x80)) {
- Store (Zero, Local0)
- } Else {
- Store (One,Local0)
- }
- //
- // Shift 1 by value in register 70, Save in buffer
- //
- ShiftLeft (Local0, And (PIRD,0x0F), IRQW)
- Return (BUF0) // Return Buf0
- } // End of _CRS method
-
- Name (_PRS, ResourceTemplate()
- {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
-
- Method (_SRS,1,NotSerialized) {
- CreateWordField (ARG0, 0x01, IRQW) // IRQ low
- FindSetRightBit (IRQW, Local0)// Set IRQ
- If (LNotEqual (IRQW, Zero)) {
- And (Local0, 0x7F, Local0)
- Decrement (Local0)
- } Else {
- Or (Local0, 0x80, Local0)
- }
- Store(Local0, PIRD)
- } // End of _SRS Method
-}
-
-Device(LNKE) { // PCI IRQ link E
- Name(_HID,EISAID("PNP0C0F"))
-
- //Name(_UID, 5)
-
- Method (_STA,0,NotSerialized) {
- If (And (PIRE, 0x80)) {
- Return(0x9)
- } Else {
- Return(0xB)
- } // Don't display
- }
-
- Method (_DIS,0,NotSerialized) {
- Or (PIRE, 0x80, PIRE)
- }
-
- Method (_CRS, 0, Serialized) {
- Name (BUF0, ResourceTemplate()
- {IRQ(Level,ActiveLow,Shared){0}})
- //
- // Define references to buffer elements
- //
- CreateWordField (BUF0, 0x01, IRQW) // IRQ low
- //
- // Write current settings into IRQ descriptor
- //
- If (And (PIRE, 0x80)) {
- Store (Zero, Local0)
- } Else {
- Store (One, Local0)
- }
- //
- // Shift 1 by value in register 70, Save in buffer
- //
- ShiftLeft (Local0, And (PIRE,0x0F), IRQW)
- Return (BUF0) // Return Buf0
- } // End of _CRS method
-
- Name(_PRS, ResourceTemplate()
- {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
-
- Method (_SRS,1,NotSerialized) {
- CreateWordField (ARG0, 0x01, IRQW) // IRQ low
- FindSetRightBit (IRQW, Local0) // Set IRQ
- If (LNotEqual (IRQW, Zero)) {
- And (Local0, 0x7F, Local0)
- Decrement (Local0)
- } Else {
- Or (Local0, 0x80, Local0)
- }
- Store (Local0, PIRE)
- } // End of _SRS Method
-}
-
-Device(LNKF) { // PCI IRQ link F
- Name (_HID,EISAID("PNP0C0F"))
-
- //Name(_UID, 6)
-
- Method (_STA,0,Serialized) {
- If (And (PIRF, 0x80)) {
- Return (0x9)
- } Else {
- Return (0xB)
- } // Don't display
- }
-
- Method (_DIS,0,NotSerialized) {
- Or (PIRB, 0x80, PIRF)
- }
-
- Method (_CRS,0,Serialized) {
- Name(BUF0, ResourceTemplate()
- {IRQ(Level,ActiveLow,Shared){0}})
- //
- // Define references to buffer elements
- //
- CreateWordField (BUF0, 0x01, IRQW) // IRQ low
- //
- // Write current settings into IRQ descriptor
- //
- If (And (PIRF, 0x80)) {
- Store (Zero, Local0)
- } Else {
- Store (One, Local0)
- }
- //
- // Shift 1 by value in register 70, Save in buffer
- //
- ShiftLeft (Local0, And (PIRF, 0x0F),IRQW)
- Return (BUF0)
- } // End of _CRS method
-
- Name(_PRS, ResourceTemplate()
- {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
-
- Method (_SRS,1,NotSerialized) {
- CreateWordField (ARG0, 0x01, IRQW) // IRQ low
- FindSetRightBit (IRQW,Local0) // Set IRQ
- If (LNotEqual (IRQW,Zero)) {
- And (Local0, 0x7F,Local0)
- Decrement (Local0)
- } Else {
- Or (Local0, 0x80, Local0)
- }
- Store (Local0, PIRF)
- } // End of _SRS Method
-}
-
-Device(LNKG) { // PCI IRQ link G
- Name(_HID,EISAID("PNP0C0F"))
- //Name(_UID, 7)
- Method(_STA,0,NotSerialized) {
- If (And (PIRG, 0x80)) {
- Return (0x9)
- } Else {
- Return (0xB)
- } // Don't display
- }
-
- Method (_DIS, 0, NotSerialized) {
- Or(PIRG, 0x80,PIRG)
- }
-
- Method (_CRS,0,Serialized){
- Name(BUF0,ResourceTemplate()
- {IRQ(Level,ActiveLow,Shared){0}})
- //
- // Define references to buffer elements
- //
- CreateWordField (BUF0, 0x01, IRQW) // IRQ low
- //
- // Write current settings into IRQ descriptor
- //
- If (And(PIRG, 0x80)) {
- Store(Zero, Local0)
- } Else {
- Store(One,Local0)
- }
- //
- // Shift 1 by value in register 70, Save in buffer
- //
- ShiftLeft (Local0,And(PIRG,0x0F),IRQW)
- Return (BUF0)
- } // End of _CRS method
-
- Name (_PRS, ResourceTemplate()
- {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
-
- Method (_SRS,1,NotSerialized) {
- CreateWordField (ARG0, 0x01, IRQW) // IRQ low
- FindSetRightBit(IRQW,Local0) // Set IRQ
- If (LNotEqual (IRQW,Zero)) {
- And (Local0, 0x7F,Local0)
- Decrement (Local0)
- } Else {
- Or (Local0, 0x80,Local0)
- }
- Store (Local0, PIRG)
- } // End of _SRS Method
-}
-
-Device(LNKH) { // PCI IRQ link H
- Name (_HID,EISAID("PNP0C0F"))
-
- //Name(_UID, 8)
-
- Method (_STA,0,Serialized) {
- If (And(PIRH, 0x80)) {
- Return(0x9)
- } Else {
- Return(0xB)
- } // Don't display
- }
-
- Method (_DIS,0,NotSerialized) {
- Or(PIRH, 0x80,PIRH)
- }
-
- Method (_CRS,0,Serialized) {
- Name(BUF0, ResourceTemplate()
- {IRQ(Level,ActiveLow,Shared){0}})
- //
- // Define references to buffer elements
- //
- CreateWordField (BUF0, 0x01, IRQW) // IRQ low
- //
- // Write current settings into IRQ descriptor
- //
- If (And (PIRH, 0x80)) {
- Store (Zero, Local0)
- } Else {
- Store (One,Local0)
- }
- //
- // Shift 1 by value in register 70, Save in buffer
- //
- ShiftLeft (Local0,And(PIRH,0x0F),IRQW)
- Return (BUF0)
- } // End of _CRS method
-
- Name(_PRS, ResourceTemplate()
- {IRQ(Level,ActiveLow,Shared){3,4,5,6,7,9,10,11,12,14,15}})
-
- Method (_SRS,1,NotSerialized) {
- CreateWordField (ARG0, 0x01, IRQW) // IRQ low
- FindSetRightBit (IRQW,Local0)// Set IRQ
- If (LNotEqual (IRQW,Zero)) {
- And (Local0, 0x7F,Local0)
- Decrement (Local0)
- } Else {
- Or (Local0, 0x80,Local0)
- }
- Store (Local0, PIRH)
- }
-}
diff --git
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHp.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHp.asi
deleted file mode 100644
index ced2b3ecd1..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHp.asi
+++ /dev/null
@@ -1,644 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
- //
- // BIOS parameter
- // The address will be fixed dynamically during boot.
- // Will be updated by ACPI platform driver as "FIX8"
- //
- OperationRegion (MCTL, SystemMemory, 0x38584946, 0x04)
- Field (MCTL, ByteAcc, NoLock, Preserve) {
- , 3,
- HGPE, 1,
- , 7,
- , 8,
- , 8
- }
-
-//
-// No longer needed, See PPA4
-//
-// OperationRegion (PSTS, PCI_Config, 0xB0, 0x04)
-// Field (PSTS, ByteAcc, NoLock, Preserve) {
-// , 16,
-// PMES, 1, // PME Status bit 16
-// PMEP, 1, //PME Pending bit 17
-// , 14
-// }
-
-
- Method (_INI, 0, NotSerialized) {
- Store (0x01, HGPE) //enable GPE message generation for ACPI
hotplug support
- }
-
- Name(_HPP, Package(){0x08, 0x40, 1, 0})
-
- //
- // begin hotplug code
- //
- Name(SHPC, 0x40) // Slot Hot-plug Capable
-
- Name(SPDS, 0x040) // Slot Presence Detect State
-
- Name(MRLS, 0x0) // MRL Closed, Standby Power to slot is on
- Name(CCOM, 0x010) // Command Complete
- Name(SPDC, 0x08) // Slot Presence Detect Changes
- Name(MRLC, 0x04) // Slot MRL Changed
- Name(SPFD, 0x02) // Slot Power Fault Detected
- Name(SABP, 0x01) // Slot Attention Button Pressed
-
- Name(SPOF, 0x10) // Slot Power Off
- Name(SPON, 0x0F) // Slot Power On Mask
-
- Name(ALMK, 0x1C) // Slot Atten. LED Mask
- Name(ALON, 0x01) // Slot Atten. LED On
- Name(ALBL, 0x02) // Slot Atten LED Blink
- Name(ALOF, 0x03) // Slot Atten LED Off
-
- Name(PLMK, 0x13) // Slot Pwr. LED Mask
- Name(PLON, 0x04) // Slot Pwr. LED On
- Name(PLBL, 0x08) // Slot Pwr. LED Blink
- Name(PLOF, 0x0C) // Slot Pwr. LED Off
-
- //;*************************************
- //; Bit 3 = Presence Detect Event
- //; Bit 2 = MRL Sensor Event
- //; Bit 1 = PWR Fault Event
- //; Bit 0 = Attention Button Event
- //;*************************************
- Name(HPEV, 0xF) // Possible interrupt events (all)
-
- //;************************************************************************;
- //;
- //; PCIe Link Control Register A0-A1h
- //;
- //; Bit - 4 - Link disable.
- //;
- //;************************************************************************;
-//
-// No longer needed, see PPA4
-//
-// OperationRegion(PPA0, PCI_Config, 0xA0, 0x02)
-// Field(PPA0,ByteAcc,NoLock,Preserve) {
-// ,4,
-// LDIS,1, // Link Disable bit4.
-// ,11,
-// }
-
- //;************************************************************************;
- //;
- //; PCIe Slot Capabilities Register A4-A7h
- //; Bit - 31-5 - Not used
- //; Bit - 4 - Power Indicator Present.
- //; Bit - 3 - Attention Indicator Present.
- //; Bit - 2 - MRL Sensor Present.
- //; Bit - 1 - Power Controller Present.
- //; Bit - 0 - Attention Button Present.
- //;
- //; PCIe Slot control Register A8-A9h
- //;
- //; Bit - 10 - PWR Control Disable
- //; Bit - 9:8 - Attn Indicator
- //; Bit - 7:6 - PWR Indicator
- //; Bit - 5 - Hot-Plug Interrupt Event Enable
- //; Bit - 4 - Command Complete Interrupt enable
- //; Bit - 3 - Presence Detect Changed Interrupt enable
- //; Bit - 2 - MRL Sensor Changed Interrupt enable
- //; Bit - 1 - PwrFault Detect Interrupt enable
- //; Bit - 0 - Attention Button Pressed Interrupt Enable
- //;
- //; PCIe Slot Status Registers AA-ADh
- //;
- //; Bit - 6 - Presence Detect State.
- //; Bit - 5 - MRL Sensor State.
- //; Bit - 4 - Command Completed.
- //;
- //; RWC Status Bits
- //;
- //; Bit - 3 - Presence Detect Changed.
- //; Bit - 2 - MRL Sensor Changed.
- //; Bit - 1 - Power Fault Detected.
- //; Bit - 0 - Attention Button Pressed.
- //;************************************************************************;
- OperationRegion(PPA4, PCI_Config, 0x00, 0x100)
- Field(PPA4,ByteAcc,NoLock,Preserve) {
- Offset (0xA0), // from PPA0 OpRegion
- ,4,
- LDIS,1, // Link Disable bit4.
- ,11,
- Offset(0xA4), // A4-A7h PCI Slot Capabilities Register
- ATBP,1, // Attention Button Present
- ,1, // Skip Power Controller Present
- MRSP,1, // MRL Sensor Present
- ATIP,1, // Attention Indicator Present
- PWIP,1, // Power Indicator Present
- ,14,
- PSNM,13, // Physical Slot Number
- Offset(0xA8), // PCIE Slot Control Register
- ABIE,1, // Attention Button Pressed Interrupt Enable
- PFIE,1, // Power Fault Detected Interrupt Enable
- MSIE,1, // MRL Sensor Changed Interrupt Enable
- PDIE,1, // Presence Detect Changed Interrupt Enable.
- CCIE,1, // Command Complete Interrupt Enable.
- HPIE,1, // Hot-plug Interrupt Enable.
- SCTL,5, // Attn/Power indicator and Power controller.
- ,5, // reserved
- Offset(0xAA), // PCIE Slot Status Register
- SSTS,7, // The status bits in Slot Status Reg
- ,1,
- Offset (0xB0), // from PSTS OpRegion
- , 16,
- PMES, 1, // PME Status bit 16
- PMEP, 1, // PME Pending bit 17
- , 14
- }
-
- //
- // These Methods replace the bit field definitions in PPA8
- // that were bit fields within SCTL
- //
- Method (ATID, 0) {
- Return (And (SCTL, 0x03))
- }
-
- Method (PWID, 0) {
- Return (ShiftRight (And (SCTL, 0x0C), 2))
- }
-
- Method (PWCC, 0) {
- Return (ShiftRight (And (SCTL, 0x10), 4))
- }
-
- //
- // These methods replace the bit fields definitions in PPA8
- // that were bit fields within SSTS
- //
- Method (ABPS, 1) {
- If (LEqual (Arg0, 1)) {
- Or (SSTS, 0x01, SSTS)
- }
- Return (And (SSTS, 0x01))
- }
-
- Method (PFDS, 1) {
- If (LEqual (Arg0, 1)) {
- Or (SSTS, 0x02, SSTS)
- }
- Return (ShiftRight (And (SSTS, 0x02), 1))
- }
-
- Method (MSCS, 1) {
- If (LEqual (Arg0, 1)) {
- Or (SSTS, 0x04, SSTS)
- }
- Return (ShiftRight (And (SSTS, 0x04), 2))
- }
-
- Method (PDCS, 1) {
- If (LEqual (Arg0, 1)) {
- Or (SSTS, 0x08, SSTS)
- }
- Return (ShiftRight (And (SSTS, 0x08), 3))
- }
-
- Method (CMCS, 1) {
- If (LEqual (Arg0, 1)) {
- Or (SSTS, 0x10, SSTS)
- }
- Return (ShiftRight (And (SSTS, 0x10), 4))
- }
-
- Method (MSSC, 1) {
- If (LEqual (Arg0, 1)) {
- Or (SSTS, 0x20, SSTS)
- }
- Return (ShiftRight (And (SSTS, 0x20), 5))
- }
-
- Method (PRDS, 1) {
- If (LEqual (Arg0, 1)) {
- Or (SSTS, 0x40, SSTS)
- }
- Return (ShiftRight (And (SSTS, 0x40), 6))
- }
-
-
-// OperationRegion(PPA8, PCI_Config, 0x00, 0x0ff)
-// Field(PPA8,ByteAcc,NoLock,Preserve) {
-// Offset(0xA8), // PCIE Slot Control Register
-// ,6,
-// ATID,2, // Attention Indicator Control.
-// PWID,2, // Power Indicator Control.
-// PWCC,1, // Power Controller Control.
-// ,5,
-// Offset(0xAA), // RWC status
-// ABPS,1, // Attention Button Pressed Status (RWC)
-// PFDS,1, // Power Fault Detect Status (RWC)
-// MSCS,1, // MRL Sensor Changed Status
-// PDCS,1, // Presence Detect Changed Status
-// CMCS,1, // Command Complete Status
-// MSSC,1, // MRL Sensor State
-// PRDS,1, // Presence Detect State
-// ,1,
-// }
-
- //;************************************************************************;
- //; This OSHP (Operating System Hot Plug) method is provided for each HPC
- //; which is controlled by ACPI. This method disables ACPI access to the
- //; HPC and restores the normal System Interrupt and Wakeup Signal
- //; connection.
- //;************************************************************************;
- Method(OSHP) { // OS call to unhook Legacy ASL PCI-Express HP
code.
- Store(0, SSTS) // Clear any status
- Store(0x0, HGPE) // Disable GPE generation
- }
-
- //;************************************************************************;
- //; Hot Plug Controller Command Method
- //;
- //; Input: Arg0 - Command to issue
- //;
- //;************************************************************************;
- Method(HPCC,1) {
- Store(SCTL, Local0) // get current command state
- Store(0, Local1) // reset the timeout value
- If(LNotEqual(Arg0, Local0)) { // see if state is different
- Store(Arg0, SCTL) // Update the Slot Control
- While(LAnd (LNot(CMCS(0)), LNotEqual(100, Local1))) { // spin while CMD
complete bit is not set,
- // check for
timeout to avoid dead loop
- Store(0xFB, IO80)
- Sleep(2) // allow processor time slice
- Add(Local1, 2, Local1)
- }
- CMCS(1) // Clear the command complete status
- }
- }
-
- //;************************************************************************;
- //; Attention Indicator Command
- //;
- //; Input: Arg0 - Command to issue
- //; 1 = ON
- //; 2 = Blink
- //; 3 = OFF
- //;************************************************************************;
- Method(ATCM,1) {
- Store(SCTL, Local0) // Get Slot Control
- And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits
- If(LEqual(Arg0, 0x1)){ // Attenion indicator "ON?"
- Or(Local0, ALON, Local0) // Set the Attention Indicator to "ON"
- }
- If(LEqual(Arg0, 0x2)){ // Attenion indicator "BLINK?"
- Or(Local0, ALBL, Local0) // Set the Attention Indicator to "BLINK"
- }
- If(LEqual(Arg0, 0x3)){ // Attenion indicator "OFF?"
- Or(Local0, ALOF, Local0) // Set the Attention Indicator to "OFF"
- }
- HPCC(Local0)
- }
-
- //;************************************************************************;
- //; Power Indicator Command
- //;
- //; Input: Arg0 - Command to issue
- //; 1 = ON
- //; 2 = Blink
- //; 3 = OFF
- //;************************************************************************;
- Method(PWCM,1){
- Store(SCTL, Local0) // Get Slot Control
- And(Local0, PLMK, Local0) // Mask the Power Indicator Bits
- If(LEqual(Arg0, 0x1)){ // Power indicator "ON?"
- Or(Local0, PLON, Local0) // Set the Power Indicator to "ON"
- }
- If(LEqual(Arg0, 0x2)){ // Power indicator "BLINK?"
- Or(Local0, PLBL, Local0) // Set the Power Indicator to "BLINK"
- }
- If(LEqual(Arg0, 0x3)){ // Power indicator "OFF?"
- Or(Local0, PLOF, Local0) // Set the Power Indicator to "OFF"
- }
- HPCC(Local0)
- }
-
- //;************************************************************************;
- //; Power Slot Command
- //;
- //; Input: Arg0 - Command to issue
- //; 1 = Slot Power ON
- //; 2 = Slot Power Off
- //;************************************************************************;
- Method(PWSL,1){
- Store(SCTL, Local0) // Get Slot Control
- If(Arg0){ // Power Slot "ON" Arg0 = 1
- And(Local0, SPON, Local0) // Turns the Power "ON"
- } Else { // Power Slot "OFF"
- Or(Local0, SPOF, Local0) // Turns the Power "OFF"
- }
- HPCC(Local0)
- }
-
- //;************************************************************************;
- //; _OST Methods to indicate that the device Eject/insert request is
- //; pending, OS could not complete it
- //;
- //; Input: Arg0 - Value used in Notify to OS
- //; 0x00 - card insert
- //; 0x03 - card eject
- //; Arg1 - status of Notify
- //; 0 - success
- //; 0x80 - Ejection not supported by OSPM
- //; 0x81 - Device in use
- //; 0x82 - Device Busy
- //; 0x84 - Ejection in progress-pending
- //;************************************************************************;
- Method(_OST,3,Serialized) {
- Switch(And(Arg0,0xFF)) { // Mask to retain low byte
- Case(0x03) { // Ejection Request
- Switch(ToInteger(Arg1)) {
- Case(Package() {0x80, 0x81, 0x82, 0x83}) {
- //
- // Ejection Failure for some reason
- //
- If (Lnot(PWCC())) { // if slot is powered
- PWCM(0x1) // Set PowerIndicator to ON
- Store(0x1,ABIE) // Set AttnBtn Interrupt ON
- }
- }
- }
- }
- }
- } // End _OST
-
- //;************************************************************************;
- //; Eject Control Methods to indicate that the device is hot-ejectable and
- //; should "eject" the device.
- //;
- //;
- //;************************************************************************;
- Method(EJ0L){
- Store(0xFF, IO80)
- Store(SCTL, Local0) // Get IIO Port Control state
- if( LNot( LEqual( ATID(), 1))) { // Check if Attention LED is not solid
"ON"
- And(Local0, ALMK, Local0) // Mask the Attention Indicator Bits
- Or(Local0, ALBL, Local0) // Set the Attention Indicator to blink
- }
- HPCC(Local0) // issue command
-
- Store(SCTL, Local0) // Get IIO Port Control state
- Or(Local0, SPOF, Local0) // Set the Power Controller Control to
Power Off
- HPCC(Local0)
-
- Store(SCTL, Local0) // Get IIO Port Control state
- Or(Local0, PLOF, Local0) // Set the Power Indicator to Off.
- HPCC(Local0)
-
- Store(SCTL, Local0) // Get IIO Port Control state
- Or(Local0, ALOF, Local0) // Set the Attntion LED to Off.
- HPCC(Local0)
-
- } // End of EJ0L
-
- //;************************************************************************;
- //; PM_PME Wake Handler for All Slots
- //;
- //; Input: Arg0 - Slot Numnber
- //;
- //;************************************************************************;
- Method(PMEH,1){ // Handler for PCI-E PM_PME Wake
Event/Interupt (GPI xxh)
- If(And(HPEV, SSTS)){ // Check for Hot-Plug Events
- If(ABPS(0)) {
- Store (Arg0, IO80) // Send slot number to Port 80
- ABPS(1) // Clear the interrupt status
- Sleep(200) // delay 200ms
- }
- }
- Return (0xff) // Indicate that this controller did not
interrupt
- } // End of Method PMEH
-
- //;************************************************************************;
- //; Hot-Plug Handler for All Slots.
- //;
- //; Input: Arg0 - Slot Number
- //;
- //;************************************************************************;
- Method(HPEH,1){ // Handler for PCI-E Hot-Plug
Event/Interupt (GPI xxh)
- Store(0xFE, IO80)
- Sleep(100)
- Store(0,CCIE) // Disable command interrupt
- If(And(HPEV, SSTS)){ // Check for Hot-Plug Events
- Store(0xFD, IO80)
- Sleep(10)
- Store (Arg0, IO80) // Send slot number to Port 80
- Sleep(10)
- Store(PPXH(), Local0) // Call Hot plug Interrupt Handler
- Return(Local0) // Return PPXH information
- }
- Else{
- Return (0xff) // Indicate that this controller did not
interrupt
- }
- Store(0xFC, IO80)
- Sleep(10)
- } // End of Method HPEH
-
- //;************************************************************************;
- //; Interrut Event Handler
- //;
- //;
- //;************************************************************************;
- Method(PPXH){ // Hot plug Interrupt Handler
- //
- // Check for the Atention Button Press, Slot Empty/Presence, Power
Controller Control.
- //
- Sleep(200) // HW Workaround for AttentionButton
Status to stabilise
- If(ABPS(0)) { // Check if Attention Button Pressed
- If(LNot(PRDS(0))) { // See if nothing installed (no card in
slot)
- Store(0x1, LDIS) // Disable the Link associated with
PCI-E port
- PWSL(0x0) // make sure Power is Off
- PWCM(0x3) // Set Power Indicator to "OFF"
- //
- // Check for MRL here and set attn indicator accordingly
- //
- If(LEqual(MSSC(0),MRLS)) { // Standby power is on - MRL closed
- ATCM(0x2) // Set Attention Indicator to "BLINK"
- } else { // Standby power is off - MRL open
- ATCM(0x3) // set attention indicator "OFF"
- }
- Store(0x0, ABIE) // set Attention Button Interrupt to
disable
- ABPS(1) // Clear the interrupt status
- Sleep(200) // delay 200ms
- Return(0xff) // Attn Button pressed without card in
slot. Do nothing
- }
- //
- // Card is present in slot so....
- //
- Store(0x0, ABIE) // set Attention Button Interrupt to
disable
- // Attn Btn Interrupt has to be enabled
only after an insert oprn
- ABPS(1) // Clear the interrupt status
- Sleep(200) // delay 200ms
- //
- // Check for MRL here - only if SPWR is OFF blink AttnInd and retun 0xff
- //
- //If(LNot(LEqual(MSSC()),MRLS))) { // Standby power is off
- // PWSL(0x0) // make sure Power is Off
- // PWCM(0x3) // Set Power Indicator to "OFF"
- // ATCM(0x2) // Set Attention Indicator to "BLINK"
- // Return(0xff) // Attn Button pressed with card in
slot, but MRL open. Do nothing
- //}
- //Card Present, if StandbyPwr is ON proceed as below with Eject Sequence
- If(PWCC()) { // Slot not Powered
- PWCM(0x3) // Set Power Indicator to "OFF"
- ATCM(0x2) // Set Attention Indicator to "BLINK"
- Return(0xff) // Attn Button pressed with card in
slot, MRL closed, Slot not powered. Do nothing
- } Else { // See if Slot is already Powered
- PWCM(0x2) // Set power Indicator to BLINK
- Sleep(600) // Wait 100ms
- Store(600, Local0) // set 5 second accumulator to 0
- ABPS(1) // Clear the interrupt status
- Sleep(200) // delay 200ms
- While(LNot(ABPS(0))) { // check for someone pressing
Attention
- Sleep(200) // Wait 200ms
- Add(Local0, 200, Local0)
- If(LEqual(5000, Local0)) { // heck if 5sec has passed without
pressing attnetion btn
- ABPS(1) // Clear the interrupt status
- Sleep(200) // delay 200ms
- Return (0x3) // continue with Eject request
- }
- }
- PWCM(0x1) // Set power Indicator baCK "ON"
- ABPS(1) // Clear the Attention status
- Sleep(200) // delay 200ms
- Store(0x1, ABIE) // set Attention Button Interrupt to
enable
- Return (0xff) // do nothing and abort
- }
- } // End if for the Attention Button Hot Plug Interrupt.
-
- If(PFDS(0)) { // Check if Power Fault Detected
- PFDS(1) // Clear the Power Fault Status
- PWSL(0x0) // set Power Off
- PWCM(0x3) // set power indicator to OFF
- ATCM(0x1) // set attention indicator "ON"
- Store(0x1, LDIS) // Disable the Link associated with
PCI-E port
- Return(0x03) // Eject request.
- } // End if for the Power Fault Interrupt.
-
- If(MSCS(0)) { // Check interrupt caused by the MRL
Sensor
- MSCS(1) // Clear the MRL Status
- If(LEqual(MSSC(0),MRLS)) { // Standby power is on - MRL closed
- If(PRDS(0)) { // Card is Present
-
- ATCM(0x3) // Set Attention Indicator to off
- PWCM(0x2) // Set Power Indicator to Blink
- Sleep(600) // Wait 100ms
- Store(600, Local0) // set 5 second accumulator to 0
- ABPS(1) // Clear the interrupt status
- While(LNot(ABPS(0))) { // check for someone pressing
Attention
- Sleep(200) // Wait 200ms
- Add(Local0, 200, Local0)
- If(LEqual(5000, Local0)) { // Check if 5 sec elapsed
- Store(0x1, ABIE) // Enable Attention button interrupt
- ATCM(0x3) // set attention indicator "OFF"
- Store(0x0, LDIS) // Enable the Link associated with PCI-E
port
- PWSL(0x1) // Power the Slot
- Sleep(500) // Wait for .5 Sec for the Power to
Stabilize.
- // Check for the Power Fault Detection
- If(LNot(PFDS(0))) { // No Power Fault
- PWCM(0x1) // Set Power Indicator to "ON"
- // Or(LVLS, 0x000010000, LVLS) // Enable the Device 4 Slot
Clock (GPIO16)
- // Notify the OS to load the Driver for the card
- Store(0x00, Local1)
- Store(0x1, ABIE) // Enable Attention button
interrupt
- } Else { // Power Fault present
- PWSL(0x0) // set Slot Power Off
- PWCM(0x3) // set power indicator to OFF
- ATCM(0x1) // set attention indicator "ON"
- Store(0x1, LDIS) // Disable the Link associated
with PCI-E port
- // And (LVLS, 0x0FFFEFFFF, LVLS) // Disable the Device 4 Slot
Clock (GPIO16)
- Store(0x03, Local1) // Eject request.
- } // End if for the Slot Power
Fault
- ABPS(1) // Clear the Attention status
- Sleep(200) // delay 200ms
- Return(Local1)
- }
- }
- //
- // someone pressed Attention Button
- //
- ABPS(1) // Clear the Attention status
- Sleep(200) // delay 200ms
- PWSL(0x0) // Set Slot Power off
- PWCM(0x3) // Set Power Indicator back to "OFF"
- ATCM(02) // Set Attention Indicator to "BLINK"
- Store(0x1, LDIS) // Disable the Link associated with PCI-E
port
- Return(0xff) // leave it off
- // End of Insert sequence
- }
- //MRL is closed, Card is not present
- PWSL(0x0) // Set Slot Power off
- PWCM(0x3) // Set Power Indicator back to "OFF"
- ATCM(02) // Set Attention Indicator to "BLINK"
- Store(0x1, LDIS) // Disable the Link associated with PCI-E
port
- Return(0xff) // leave it off
- } Else { // MRL is open i.e Stdby power is turned
off
- If(PRDS(0)) { //card present MRL switched off
- ATCM(0x2) // Set Attention Indicator to "BLINK"
- If(Lnot(PWCC())) { // If slot is powered
- // This event is not supported and someone has opened the MRL and
dumped the power
- // on the slot with possible pending transactions. This could
hose the OS.
- // Try to Notify the OS to unload the drivers.
- PWSL(0x0) // Set Slot Power off
- PWCM(0x3) // Set Power Indicator back to "OFF"
- Store(0x1, LDIS) // Disable the Link associated with PCI-E
port
- Return(0x03) // Eject request.
- } Else { // Slot not powered, MRL is opened, card
still in slot - Eject not fully complete
- Return(0xFF)
- }
- }
- //no card present and Stdby power switched off, turn AI off
- ATCM(0x3) // Set Attention Indicator to "OFF"
- Return(0xff) // leave it off
- } // End of MRL switch open/close state
- } // End of MRL Sensor State Change
-
- If(PDCS(0)) { // Check if Presence Detect Changed Status
- PDCS(1) // Clear the Presence Detect Changed Status
- If(LNot(PRDS(0))) { // Slot is Empty
- PWSL(0x0) // Set Slot Power "OFF"
- PWCM(0x3) // set power indicator to "OFF"
- If(LEqual(MSSC(0),MRLS)) { // If Standby power is on
- ATCM(0x2) // Set Attention Indicator to "Blink"
- } else {
- ATCM(0x3) // Set Attention Indicator to "OFF"
- }
- Store(0x1, LDIS) // Disable the Link associated with PCI-E
port
- Return(0xFF) // Do nothing
- } Else { // Slot Card is inserted
- // Irrespective of MRL state, do the following
- Store(0x0, LDIS) // Enable the Link associated with PCI-E
port
- PWSL(0x1) // Set Slot Power ON
- Sleep(500) // Wait for .5 Sec for the Power to
Stabilize.
- If(LNot(PFDS(0))) { // No Power Fault
- PWCM(0x1) // Set Power Indicator to "ON"
- Store(0x00, Local1)
- Store(0x1, ABIE) // Enable Attention button interrupt
- ATCM(0x3) // Set Attention Indicator to "OFF"
- } Else { // Power Fault present
- PWSL(0x0) // set Slot Power Off
- PWCM(0x3) // set power indicator to OFF
- ATCM(0x1) // set attention indicator "ON"
- Store(0x1, LDIS) // Disable the Link associated with PCI-E
port
- Store(0x03, Local1) // Eject request.
- } // End if for the Slot Power Fault
- ABPS(1) // Clear the Attention status
- Sleep(200) // delay 200ms
- Return(Local1)
- }
- } // End if for the Presence Detect Changed Hot Plug Interrupt.
- Return(0xff) // should not get here, but do device check if it does.
- } // End of method PP5H
- //
- // End of hotplug code
- //
diff --git
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHpDev.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHpDev.asi
deleted file mode 100644
index 34feaa8137..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieHpDev.asi
+++ /dev/null
@@ -1,14 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
- Method(SNUM, 0, Serialized) {
- Store(PSNM, Local0)
- Return(Local0)
- }
-
- Method(_SUN, 0) { Return(SNUM) } // Slot User Number
- Method(_EJ0, 1) { EJ0L() } // Remove all power from the slot
diff --git
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieNonHpDev.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieNonHpDev.asi
deleted file mode 100644
index c990898e87..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieNonHpDev.asi
+++ /dev/null
@@ -1,16 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
- Method(SNUM, 0, Serialized) {
- Store(PSNM, Local0)
- Return(Local0)
- }
-
- Method(_SUN, 0) {
- Return(SNUM)
- } // Slot User Number
-
diff --git
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieSeg.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieSeg.asi
deleted file mode 100644
index 51c919f5e5..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PcieSeg.asi
+++ /dev/null
@@ -1,355 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-#include "MaxSocket.h"
-
- Scope(\) {
-
- //
- // \SG00, SG01,... SG07 are defined to contain Segment # for
Segment/socket 0, 1, ....
- //
- // Create _SEG for each segment/socket
- //
-
- //
- // Debug method for use under BITS
- // Example: Set SG01 to 5 SSEG(1,5)
- //
- Method(SSEG, 2) {
- If (LEqual(Arg0, 0) ) { Store (Arg1, SG00) }
- If (LEqual(Arg0, 1) ) { Store (Arg1, SG01) }
- If (LEqual(Arg0, 2) ) { Store (Arg1, SG02) }
- If (LEqual(Arg0, 3) ) { Store (Arg1, SG03) }
- }
-
-
-// ------------------------------------------------------
-// Socket 0 PC00 - PC05 share the same segment number SG00
-// ------------------------------------------------------
-
- Scope(\_SB.PC00) {
- Method (_SEG, 0, NotSerialized) {
- return (SG00)
- }
- }
-
- Scope(\_SB.PC01) {
- Method (_SEG, 0, NotSerialized) {
- return (SG00)
- }
- }
-
- Scope(\_SB.PC02) {
- Method (_SEG, 0, NotSerialized) {
- return (SG00)
- }
- }
-
- Scope(\_SB.PC03) {
- Method (_SEG, 0, NotSerialized) {
- return (SG00)
- }
- }
-
- Scope(\_SB.PC04) {
- Method (_SEG, 0, NotSerialized) {
- return (SG00)
- }
- }
-
- Scope(\_SB.PC05) {
- Method (_SEG, 0, NotSerialized) {
- return (SG00)
- }
- }
-
-// ------------------------------------------------------
-// Socket 1 PC06 - PC11 share the same segment number SG01
-// ------------------------------------------------------
-
- Scope(\_SB.PC06) {
- Method (_SEG, 0, NotSerialized) {
- return (SG01)
- }
- }
-
- Scope(\_SB.PC07) {
- Method (_SEG, 0, NotSerialized) {
- return (SG01)
- }
- }
-
- Scope(\_SB.PC08) {
- Method (_SEG, 0, NotSerialized) {
- return (SG01)
- }
- }
-
- Scope(\_SB.PC09) {
- Method (_SEG, 0, NotSerialized) {
- return (SG01)
- }
- }
-
- Scope(\_SB.PC10) {
- Method (_SEG, 0, NotSerialized) {
- return (SG01)
- }
- }
-
- Scope(\_SB.PC11) {
- Method (_SEG, 0, NotSerialized) {
- return (SG01)
- }
- }
-
-// ------------------------------------------------------
-// Socket 2 PC12 - PC17 share the same segment number SG02
-// ------------------------------------------------------
-
- Scope(\_SB.PC12) {
- Method (_SEG, 0, NotSerialized) {
- return (SG02)
- }
- }
-
- Scope(\_SB.PC13) {
- Method (_SEG, 0, NotSerialized) {
- return (SG02)
- }
- }
-
- Scope(\_SB.PC14) {
- Method (_SEG, 0, NotSerialized) {
- return (SG02)
- }
- }
-
- Scope(\_SB.PC15) {
- Method (_SEG, 0, NotSerialized) {
- return (SG02)
- }
- }
-
- Scope(\_SB.PC16) {
- Method (_SEG, 0, NotSerialized) {
- return (SG02)
- }
- }
-
- Scope(\_SB.PC17) {
- Method (_SEG, 0, NotSerialized) {
- return (SG02)
- }
- }
-
-
-// ------------------------------------------------------
-// Socket 3 PC18 - PC23 share the same segment number SG03
-// ------------------------------------------------------
-
- Scope(\_SB.PC18) {
- Method (_SEG, 0, NotSerialized) {
- return (SG03)
- }
- }
-
- Scope(\_SB.PC19) {
- Method (_SEG, 0, NotSerialized) {
- return (SG03)
- }
- }
-
- Scope(\_SB.PC20) {
- Method (_SEG, 0, NotSerialized) {
- return (SG03)
- }
- }
-
- Scope(\_SB.PC21) {
- Method (_SEG, 0, NotSerialized) {
- return (SG03)
- }
- }
-
- Scope(\_SB.PC22) {
- Method (_SEG, 0, NotSerialized) {
- return (SG03)
- }
- }
-
- Scope(\_SB.PC23) {
- Method (_SEG, 0, NotSerialized) {
- return (SG03)
- }
- }
-
-#if MAX_SOCKET > 4
-
-// ------------------------------------------------------
-// Socket 4 PC24 - PC29 share the same segment number SG03
-// ------------------------------------------------------
-
- Scope(\_SB.PC24) {
- Method (_SEG, 0, NotSerialized) {
- return (SG04)
- }
- }
-
- Scope(\_SB.PC25) {
- Method (_SEG, 0, NotSerialized) {
- return (SG04)
- }
- }
-
- Scope(\_SB.PC26) {
- Method (_SEG, 0, NotSerialized) {
- return (SG04)
- }
- }
-
- Scope(\_SB.PC27) {
- Method (_SEG, 0, NotSerialized) {
- return (SG04)
- }
- }
-
- Scope(\_SB.PC28) {
- Method (_SEG, 0, NotSerialized) {
- return (SG04)
- }
- }
-
- Scope(\_SB.PC29) {
- Method (_SEG, 0, NotSerialized) {
- return (SG04)
- }
- }
-
-// ------------------------------------------------------
-// Socket 5 PC30 - PC35 share the same segment number SG03
-// ------------------------------------------------------
-
- Scope(\_SB.PC30) {
- Method (_SEG, 0, NotSerialized) {
- return (SG05)
- }
- }
-
- Scope(\_SB.PC31) {
- Method (_SEG, 0, NotSerialized) {
- return (SG05)
- }
- }
-
- Scope(\_SB.PC32) {
- Method (_SEG, 0, NotSerialized) {
- return (SG05)
- }
- }
-
- Scope(\_SB.PC33) {
- Method (_SEG, 0, NotSerialized) {
- return (SG05)
- }
- }
-
- Scope(\_SB.PC34) {
- Method (_SEG, 0, NotSerialized) {
- return (SG05)
- }
- }
-
- Scope(\_SB.PC35) {
- Method (_SEG, 0, NotSerialized) {
- return (SG05)
- }
- }
-
-// ------------------------------------------------------
-// Socket 6 PC36 - PC41 share the same segment number SG03
-// ------------------------------------------------------
-
- Scope(\_SB.PC36) {
- Method (_SEG, 0, NotSerialized) {
- return (SG06)
- }
- }
-
- Scope(\_SB.PC37) {
- Method (_SEG, 0, NotSerialized) {
- return (SG06)
- }
- }
-
- Scope(\_SB.PC38) {
- Method (_SEG, 0, NotSerialized) {
- return (SG06)
- }
- }
-
- Scope(\_SB.PC39) {
- Method (_SEG, 0, NotSerialized) {
- return (SG06)
- }
- }
-
- Scope(\_SB.PC40) {
- Method (_SEG, 0, NotSerialized) {
- return (SG06)
- }
- }
-
- Scope(\_SB.PC41) {
- Method (_SEG, 0, NotSerialized) {
- return (SG06)
- }
- }
-
-// ------------------------------------------------------
-// Socket 7 PC42 - PC47 share the same segment number SG03
-// ------------------------------------------------------
-
- Scope(\_SB.PC42) {
- Method (_SEG, 0, NotSerialized) {
- return (SG07)
- }
- }
-
- Scope(\_SB.PC43) {
- Method (_SEG, 0, NotSerialized) {
- return (SG07)
- }
- }
-
- Scope(\_SB.PC44) {
- Method (_SEG, 0, NotSerialized) {
- return (SG07)
- }
- }
-
- Scope(\_SB.PC45) {
- Method (_SEG, 0, NotSerialized) {
- return (SG07)
- }
- }
-
- Scope(\_SB.PC46) {
- Method (_SEG, 0, NotSerialized) {
- return (SG07)
- }
- }
-
- Scope(\_SB.PC47) {
- Method (_SEG, 0, NotSerialized) {
- return (SG07)
- }
- }
-#endif
-
-} // End Scope(\)
-
diff --git
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi
deleted file mode 100644
index 1f3087a7b3..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/PlatformGpe.asi
+++ /dev/null
@@ -1,78 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
-// General Purpose Event
-#include "MaxSocket.h"
-
-Scope (\_GPE) {
-
- //
- // ME HECI2 SCI handler
- // Note: This SCI from HECI2 is routed to ICH9 over the DMI and it
- // sets the DMISCI status bit in TCO block. From there it is routed
- // to bit6 GPE0 status register.
- //
- OperationRegion (TCOS, SystemIO, 0x464, 2) // ICH_ACPI_BASE_ADDRESS +
TCO_BASE + R_TCO1_STS
- Field (TCOS, ByteAcc, NoLock, WriteAsZeros) {
- Offset (0x1),
- , 1,
- DSCI, 1,
- }
-
- Method(NTFI, 2){
- If(And(Arg0, 0x01)){
- Notify(\_SB.PC06, Arg1)
- Notify(\_SB.PC07, Arg1)
- Notify(\_SB.PC08, Arg1)
- Notify(\_SB.PC09, Arg1)
- Notify(\_SB.PC10, Arg1)
- Notify(\_SB.PC11, Arg1)
- }
- If(And(Arg0, 0x02)){
- Notify(\_SB.PC12, Arg1)
- Notify(\_SB.PC13, Arg1)
- Notify(\_SB.PC14, Arg1)
- Notify(\_SB.PC15, Arg1)
- Notify(\_SB.PC16, Arg1)
- Notify(\_SB.PC17, Arg1)
- }
- If(And(Arg0, 0x04)){
- Notify(\_SB.PC18, Arg1)
- Notify(\_SB.PC19, Arg1)
- Notify(\_SB.PC20, Arg1)
- Notify(\_SB.PC21, Arg1)
- Notify(\_SB.PC22, Arg1)
- Notify(\_SB.PC23, Arg1)
- }
- } //End Method NTFI
-
- // Tell OS to run thru the new status of this device (Software SCI generated
from SMM for all Hot plug events)
- Method (_L62, 0x0, NotSerialized) {
- if(LEqual(SCI0, 3)) { // Device ejection (Invoked with _EJ0 method called)
- Store (0, SCI0)
- } else { // Device check (OS can still reject online request
based on resources and capability)
- NTFI (IIOP, 0)
- Store (0, MEBC)
- Store (0, CPHP)
- Store (0, IIOP)
- }
- Store (0, SGPC)
- Store (1, SGPS)
-
- }
-
- // PME supported for Slots, use GPE 9 for PME
- // Hot plug on all slots for now, change later.
- // Slot numbers on silk screen might be different than the port number,
currently use port numbers.
- //
- // IIO PCI_E Slot Hotplug GPE Event
- //
- Method (_L61, 0, NotSerialized) {
- #include "IioPcieHotPlugGpeHandler.asl"
- }// end of _L01 GPE Method
-
-}// end of _GPE scope.
diff --git
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck1Ejd.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck1Ejd.asi
deleted file mode 100644
index 2cbe3aa5cc..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck1Ejd.asi
+++ /dev/null
@@ -1,9 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
- // Eject device if SCK1 is removed.
- Name(_EJD,"\\_SB.SCK1") // Dependent on SCK1
diff --git
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck2Ejd.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck2Ejd.asi
deleted file mode 100644
index 4a89bb99d6..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck2Ejd.asi
+++ /dev/null
@@ -1,9 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
- // Eject device if SCK2 is removed.
- Name(_EJD,"\\_SB.SCK2") // Dependent on SCK2
diff --git
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck3Ejd.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck3Ejd.asi
deleted file mode 100644
index 8cbaeffeb5..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Sck3Ejd.asi
+++ /dev/null
@@ -1,9 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
- // Eject device if SCK3 is removed.
- Name(_EJD,"\\_SB.SCK3") // Dependent on SCK3
diff --git
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore0.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore0.asi
deleted file mode 100644
index a5a447d037..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore0.asi
+++ /dev/null
@@ -1,33 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
- Name (PRU0, Package() {
- Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 }
- })
-
- Name (ARU0, Package() {
- Package() { 0x0008FFFF, 0, 0, 16 },
- Package() { 0x0008FFFF, 1, 0, 17 },
- Package() { 0x0008FFFF, 2, 0, 18 },
- Package() { 0x0008FFFF, 3, 0, 19 }
- })
-
-
- Device (UNC0) {
- Name (_UID, "UNCORE0")
- Name (_ADR, 0x00000000)
- Method (_PRT, 0) {
- If (LEqual(PICM, Zero)) {
- Return (PRU0)
- }
- Return (ARU0)
- }
- }
-
diff --git
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore1.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore1.asi
deleted file mode 100644
index a86aaa7b3f..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore1.asi
+++ /dev/null
@@ -1,175 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
- Name (PRU1, Package() {
- Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
-
- Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x0011FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x0011FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x0011FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x0011FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x0014FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x0014FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x0014FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x0014FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x001DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x001DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x001DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x001DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x001EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x001EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x001EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x001EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x001FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x001FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x001FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x001FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
- })
-
- Name (ARU1, Package() {
- Package() { 0x0008FFFF, 0, 0, 16 },
- Package() { 0x0008FFFF, 1, 0, 17 },
- Package() { 0x0008FFFF, 2, 0, 18 },
- Package() { 0x0008FFFF, 3, 0, 19 },
-
- Package() { 0x0009FFFF, 0, 0, 16 },
- Package() { 0x0009FFFF, 1, 0, 17 },
- Package() { 0x0009FFFF, 2, 0, 18 },
- Package() { 0x0009FFFF, 3, 0, 19 },
-
- Package() { 0x000AFFFF, 0, 0, 16 },
- Package() { 0x000AFFFF, 1, 0, 17 },
- Package() { 0x000AFFFF, 2, 0, 18 },
- Package() { 0x000AFFFF, 3, 0, 19 },
-
- Package() { 0x000BFFFF, 0, 0, 16 },
- Package() { 0x000BFFFF, 1, 0, 17 },
- Package() { 0x000BFFFF, 2, 0, 18 },
- Package() { 0x000BFFFF, 3, 0, 19 },
-
- Package() { 0x000EFFFF, 0, 0, 16 },
- Package() { 0x000EFFFF, 1, 0, 17 },
- Package() { 0x000EFFFF, 2, 0, 18 },
- Package() { 0x000EFFFF, 3, 0, 19 },
-
- Package() { 0x000FFFFF, 0, 0, 16 },
- Package() { 0x000FFFFF, 1, 0, 17 },
- Package() { 0x000FFFFF, 2, 0, 18 },
- Package() { 0x000FFFFF, 3, 0, 19 },
-
- Package() { 0x0010FFFF, 0, 0, 16 },
- Package() { 0x0010FFFF, 1, 0, 17 },
- Package() { 0x0010FFFF, 2, 0, 18 },
- Package() { 0x0010FFFF, 3, 0, 19 },
-
- Package() { 0x0011FFFF, 0, 0, 16 },
- Package() { 0x0011FFFF, 1, 0, 17 },
- Package() { 0x0011FFFF, 2, 0, 18 },
- Package() { 0x0011FFFF, 3, 0, 19 },
-
- Package() { 0x0014FFFF, 0, 0, 16 },
- Package() { 0x0014FFFF, 1, 0, 17 },
- Package() { 0x0014FFFF, 2, 0, 18 },
- Package() { 0x0014FFFF, 3, 0, 19 },
-
- Package() { 0x0015FFFF, 0, 0, 16 },
- Package() { 0x0015FFFF, 1, 0, 17 },
- Package() { 0x0015FFFF, 2, 0, 18 },
- Package() { 0x0015FFFF, 3, 0, 19 },
-
- Package() { 0x0016FFFF, 0, 0, 16 },
- Package() { 0x0016FFFF, 1, 0, 17 },
- Package() { 0x0016FFFF, 2, 0, 18 },
- Package() { 0x0016FFFF, 3, 0, 19 },
-
- Package() { 0x0017FFFF, 0, 0, 16 },
- Package() { 0x0017FFFF, 1, 0, 17 },
- Package() { 0x0017FFFF, 2, 0, 18 },
- Package() { 0x0017FFFF, 3, 0, 19 },
-
- Package() { 0x001DFFFF, 0, 0, 16 },
- Package() { 0x001DFFFF, 1, 0, 17 },
- Package() { 0x001DFFFF, 2, 0, 18 },
- Package() { 0x001DFFFF, 3, 0, 19 },
-
- Package() { 0x001EFFFF, 0, 0, 16 },
- Package() { 0x001EFFFF, 1, 0, 17 },
- Package() { 0x001EFFFF, 2, 0, 18 },
- Package() { 0x001EFFFF, 3, 0, 19 },
-
- Package() { 0x001FFFFF, 0, 0, 16 },
- Package() { 0x001FFFFF, 1, 0, 17 },
- Package() { 0x001FFFFF, 2, 0, 18 },
- Package() { 0x001FFFFF, 3, 0, 19 },
- })
-
- //
- // Devices 8 - 31 on PStack
- //
- Device (UNC1) {
- Name (_UID, "UNCORE1")
- Name (_ADR, 0x00000000)
- Method (_PRT, 0) {
- If (LEqual(PICM, Zero)) {
- Return (PRU1)
- }
- Return (ARU1)
- }
- }
diff --git
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore2.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore2.asi
deleted file mode 100644
index dc7453c294..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore2.asi
+++ /dev/null
@@ -1,125 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
- Name (PRU2, Package() {
- //
- // PCIe2 PortA/NTB
- //
- Package() { 0x0000FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x0000FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x0000FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x0000FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x0008FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x0008FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x0008FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x0008FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x0009FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x0009FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x0009FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x0009FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x000AFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x000AFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x000AFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x000AFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x000BFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x000BFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x000BFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x000BFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x000CFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x000CFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x000CFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x000CFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x000DFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x000DFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x000DFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x000DFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
-
- Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- })
-
- Name (ARU2, Package() {
- //
- // PCIe2 PortA/NTB
- //
- Package() { 0x0000FFFF, 0, 0, 16 },
- Package() { 0x0000FFFF, 1, 0, 17 },
- Package() { 0x0000FFFF, 2, 0, 18 },
- Package() { 0x0000FFFF, 3, 0, 19 },
-
- Package() { 0x0008FFFF, 0, 0, 16 },
- Package() { 0x0008FFFF, 1, 0, 17 },
- Package() { 0x0008FFFF, 2, 0, 18 },
- Package() { 0x0008FFFF, 3, 0, 19 },
-
- Package() { 0x0009FFFF, 0, 0, 16 },
- Package() { 0x0009FFFF, 1, 0, 17 },
- Package() { 0x0009FFFF, 2, 0, 18 },
- Package() { 0x0009FFFF, 3, 0, 19 },
-
- Package() { 0x000AFFFF, 0, 0, 16 },
- Package() { 0x000AFFFF, 1, 0, 17 },
- Package() { 0x000AFFFF, 2, 0, 18 },
- Package() { 0x000AFFFF, 3, 0, 19 },
-
- Package() { 0x000BFFFF, 0, 0, 16 },
- Package() { 0x000BFFFF, 1, 0, 17 },
- Package() { 0x000BFFFF, 2, 0, 18 },
- Package() { 0x000BFFFF, 3, 0, 19 },
-
- Package() { 0x000CFFFF, 0, 0, 16 },
- Package() { 0x000CFFFF, 1, 0, 17 },
- Package() { 0x000CFFFF, 2, 0, 18 },
- Package() { 0x000CFFFF, 3, 0, 19 },
-
- Package() { 0x000DFFFF, 0, 0, 16 },
- Package() { 0x000DFFFF, 1, 0, 17 },
- Package() { 0x000DFFFF, 2, 0, 18 },
- Package() { 0x000DFFFF, 3, 0, 19 },
-
-
- Package() { 0x0016FFFF, 0, 0, 16 },
- Package() { 0x0016FFFF, 1, 0, 17 },
- Package() { 0x0016FFFF, 2, 0, 18 },
- Package() { 0x0016FFFF, 3, 0, 19 },
-
- Package() { 0x0017FFFF, 0, 0, 16 },
- Package() { 0x0017FFFF, 1, 0, 17 },
- Package() { 0x0017FFFF, 2, 0, 18 },
- Package() { 0x0017FFFF, 3, 0, 19 },
-
- })
-
- //
- // Devices 8 - 31 on each stack
- //
- Device (UNC2) {
- Name (_UID, "UNCORE2")
- Name (_ADR, 0x00000000)
- Method (_PRT, 0) {
- If (LEqual(PICM, Zero)) {
- Return (PRU2)
- }
- Return (ARU2)
- }
- }
-
diff --git
a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore3.asi
b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore3.asi
deleted file mode 100644
index f59e04539b..0000000000
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/Dsdt/Uncore3.asi
+++ /dev/null
@@ -1,98 +0,0 @@
-/** @file
-
-Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
-SPDX-License-Identifier: BSD-2-Clause-Patent
-
-**/
-
- Name (PRU3, Package() {
-
- Package() { 0x000EFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x000EFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x000EFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x000EFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x000FFFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x000FFFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x000FFFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x000FFFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x0010FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x0010FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x0010FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x0010FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
-
- Package() { 0x0012FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x0012FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x0012FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x0012FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x0015FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x0015FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x0015FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x0015FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x0016FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x0016FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x0016FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x0016FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- Package() { 0x0017FFFF, 0, \_SB.PC00.LPC0.LNKA, 0 },
- Package() { 0x0017FFFF, 1, \_SB.PC00.LPC0.LNKB, 0 },
- Package() { 0x0017FFFF, 2, \_SB.PC00.LPC0.LNKC, 0 },
- Package() { 0x0017FFFF, 3, \_SB.PC00.LPC0.LNKD, 0 },
-
- })
-
- Name (ARU3, Package() {
- Package() { 0x000EFFFF, 0, 0, 16 },
- Package() { 0x000EFFFF, 1, 0, 17 },
- Package() { 0x000EFFFF, 2, 0, 18 },
- Package() { 0x000EFFFF, 3, 0, 19 },
-
- Package() { 0x000FFFFF, 0, 0, 16 },
- Package() { 0x000FFFFF, 1, 0, 17 },
- Package() { 0x000FFFFF, 2, 0, 18 },
- Package() { 0x000FFFFF, 3, 0, 19 },
-
- Package() { 0x0010FFFF, 0, 0, 16 },
- Package() { 0x0010FFFF, 1, 0, 17 },
- Package() { 0x0010FFFF, 2, 0, 18 },
- Package() { 0x0010FFFF, 3, 0, 19 },
-
- Package() { 0x0012FFFF, 0, 0, 16 },
- Package() { 0x0012FFFF, 1, 0, 17 },
- Package() { 0x0012FFFF, 2, 0, 18 },
- Package() { 0x0012FFFF, 3, 0, 19 },
-
- Package() { 0x0015FFFF, 0, 0, 16 },
- Package() { 0x0015FFFF, 1, 0, 17 },
- Package() { 0x0015FFFF, 2, 0, 18 },
- Package() { 0x0015FFFF, 3, 0, 19 },
-
- Package() { 0x0016FFFF, 0, 0, 16 },
- Package() { 0x0016FFFF, 1, 0, 17 },
- Package() { 0x0016FFFF, 2, 0, 18 },
- Package() { 0x0016FFFF, 3, 0, 19 },
-
- Package() { 0x0017FFFF, 0, 0, 16 },
- Package() { 0x0017FFFF, 1, 0, 17 },
- Package() { 0x0017FFFF, 2, 0, 18 },
- Package() { 0x0017FFFF, 3, 0, 19 },
- })
-
- //
- // Devices 8 - 31 on each stack
- //
- Device (UNC3) {
- Name (_UID, "UNCORE3")
- Name (_ADR, 0x00000000)
- Method (_PRT, 0) {
- If (LEqual(PICM, Zero)) {
- Return (PRU3)
- }
- Return (ARU3)
- }
- }
-
--
2.16.2.windows.1
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