The RD-N2 platform includes sixteen single-thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also includes a system level cache of 32MB. Add PPTT table for RD-N2 platform with this information.
Signed-off-by: Pranav Madhu <pranav.ma...@arm.com> --- Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 3 +- Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 175 ++++++++++++++++++++ 2 files changed, 177 insertions(+), 1 deletion(-) diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf index 2ec3e42473a9..c1282a3422ab 100644 --- a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf @@ -1,7 +1,7 @@ ## @file # ACPI table data and ASL sources required to boot the platform. # -# Copyright (c) 2020, Arm Ltd. All rights reserved. +# Copyright (c) 2020-2021, Arm Ltd. All rights reserved. # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -22,6 +22,7 @@ Mcfg.aslc RdN2/Dsdt.asl RdN2/Madt.aslc + RdN2/Pptt.aslc Spcr.aslc Ssdt.asl SsdtRos.asl diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc new file mode 100644 index 000000000000..16daf5b7f266 --- /dev/null +++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc @@ -0,0 +1,175 @@ +/** @file +* Processor Properties Topology Table (PPTT) for RD-N2 platform +* +* This file describes the topological structure of the processor block on the +* RD-N2 platform in the form as defined by ACPI PPTT table. The RD-N2 platform +* includes sixteen single-thread CPUS. Each of the CPUs include 64KB L1 Data +* cache, 64KB L1 Instruction cache and 1MB L2 cache. The platform also includes +* system level cache of 32MB. +* +* Copyright (c) 2021, ARM Limited. All rights reserved. +* +* SPDX-License-Identifier: BSD-2-Clause-Patent +* +* @par Specification Reference: +* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology Table +**/ + +#include <IndustryStandard/Acpi.h> +#include <Library/AcpiLib.h> +#include <Library/ArmLib.h> +#include <Library/PcdLib.h> + +#include "SgiPlatform.h" +#include "SgiAcpiHeader.h" + +/*! + \brief Define helper macro for populating processor core information. + \param PackageId Package instance number. + \param ClusterId Cluster instance number. + \param CpuId CPU instance number. +*/ +#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) \ + { \ + /* Parameters for CPU Core */ \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \ + OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ \ + PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \ + Package.Cluster[ClusterId]), /* Parent */ \ + ((PackageId << 4) | ClusterId), /* ACPI Id */ \ + 2 /* Num of private resource */ \ + ), \ + \ + /* Offsets of the private resources */ \ + { \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \ + Package.Cluster[ClusterId].Core[CpuId].DCache), \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \ + Package.Cluster[ClusterId].Core[CpuId].ICache) \ + }, \ + \ + /* L1 data cache parameters */ \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \ + Package.Cluster[ClusterId].Core[CpuId].L2Cache), \ + /* Next level of cache */ \ + SIZE_64KB, /* Size */ \ + 256, /* Num of sets */ \ + 4, /* Associativity */ \ + PPTT_DATA_CACHE_ATTR, /* Attributes */ \ + 64 /* Line size */ \ + ), \ + \ + /* L1 instruction cache parameters */ \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \ + Package.Cluster[ClusterId].Core[CpuId].L2Cache), \ + /* Next level of cache */ \ + SIZE_64KB, /* Size */ \ + 256, /* Num of sets */ \ + 4, /* Associativity */ \ + PPTT_INST_CACHE_ATTR, /* Attributes */ \ + 64 /* Line size */ \ + ), \ + \ + /* L2 cache parameters */ \ + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( \ + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ \ + 0, /* Next level of cache */ \ + SIZE_1MB, /* Size */ \ + 2048, /* Num of sets */ \ + 8, /* Associativity */ \ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ \ + 64 /* Line size */ \ + ), \ + } + +/*! + \brief Define helper macro for populating processor container information. + \param PackageId Package instance number. + \param ClusterId Cluster instance number. +*/ +#define PPTT_CLUSTER_INIT(PackageId, ClusterId) \ + { \ + /* Parameters for Cluster */ \ + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( \ + OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ \ + PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ \ + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, \ + Package), /* Parent */ \ + ((PackageId << 4) | ClusterId), /* ACPI Id */ \ + 0 /* Num of private resource */ \ + ), \ + \ + /* Initialize child core */ \ + { \ + PPTT_CORE_INIT (PackageId, ClusterId, 0) \ + } \ + } + +#pragma pack(1) +/* + * Processor Properties Topology Table + */ +typedef struct { + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header; + RD_PPTT_SLC_PACKAGE Package; +} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE; +#pragma pack () + +STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt = { + { + ARM_ACPI_HEADER ( + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION + ) + }, + + { + EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( + OFFSET_OF (RD_PPTT_SLC_PACKAGE, Slc), + PPTT_PROCESSOR_PACKAGE_FLAGS, 0, 0, 1), + + OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, + Package.Slc), + + EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( + PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ + 0, /* Next level of cache */ + SIZE_32MB, /* Size */ + 32768, /* Num of sets */ + 16, /* Associativity */ + PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ + 64 /* Line size */ + ), + + { + PPTT_CLUSTER_INIT (0, 0), + PPTT_CLUSTER_INIT (0, 1), + PPTT_CLUSTER_INIT (0, 2), + PPTT_CLUSTER_INIT (0, 3), + PPTT_CLUSTER_INIT (0, 4), + PPTT_CLUSTER_INIT (0, 5), + PPTT_CLUSTER_INIT (0, 6), + PPTT_CLUSTER_INIT (0, 7), + PPTT_CLUSTER_INIT (0, 8), + PPTT_CLUSTER_INIT (0, 9), + PPTT_CLUSTER_INIT (0, 10), + PPTT_CLUSTER_INIT (0, 11), + PPTT_CLUSTER_INIT (0, 12), + PPTT_CLUSTER_INIT (0, 13), + PPTT_CLUSTER_INIT (0, 14), + PPTT_CLUSTER_INIT (0, 15) + } + } +}; + +/* + * Reference the table being generated to prevent the optimizer from removing + * the data structure from the executable + */ +VOID* CONST ReferenceAcpiTable = &Pptt; -- 2.17.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. 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